經過這幾年的研究，下列的事實已為人所知：電路中一特定路徑的延遲，可由電路中的其他路徑延遲線性組成。如果用來組成該特定路徑的所有路徑皆為 robust 路徑 (具有較好的測試品質)，只要經由簡單的數學運算，便可得知該特定路徑的延遲。然而，現今並沒有人提出一個完整方法來幫助我們尋找路徑集合來組合出電路中的大部分路徑延遲。因此，在這篇論文中，在給定一個主要路徑延遲集合的情況下，我們提出了一個方法，這個方法使用兩個步驟來尋找一組 robust 路徑 (數量少於電路中原本的主要 robust 路徑) 來含括電路中大部分的主要路徑。第一個步驟，先由主要 robust 路徑中挑出必需存在的路徑子集合，利用這些路徑來含括大部分的主要路徑；第二個步驟再找出非主要的 robust 路徑，來處理未被含括的主要路徑中的 functional sensitizatable segments。根據實驗結果，電路中有相當大比例 (15% - 100%，平均來說大約是 85%) 的主要路徑延遲都可由其他的路徑組合而成。在經過 octave 驗證之後，證明這些實驗結果皆正確無誤，並且已經達到最佳的結果。進一步藉由手動分析這些實驗數據，可以發現剩餘的難測試 (functional sensitizable) 路徑通常只是由於電路中數十個左右的segments所
造成 (除了s35932 這個電路之外)。對於這些造成路徑無法被含括的 segments，只要加上一些額外的面積來設計控制器，便可以利用可測試性設計技術 (DfT) 來確保電路中所有的主要路徑都可以由特定的路徑集合組合出來。

It has been shown that the delay of a target path can be composed inearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this thesis, given a set of target critical paths, we proposed a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (15%-100%, 85% on average) of critical testable paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segemnts in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads.

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