在這篇論文中，我們提出一個可調變的數位訊號處理器（Digital Signal Processor）子系統及其除錯基本架構。在國立清華大學及國立交通大學所共同研發的計劃—超低功率數位訊號處理器核心開發計劃(Starfish)中加入，並實現我們所提出的架構。
在我們所提出的子系統中，整合了包括超低功率數位訊號處理器—Starfish、記憶體管理單元，指令緩衝區，資料緩衝區，及追蹤除錯單元。為了降低資料在匯流排中傳輸造成時間的負擔，我們將記憶體系統設計成二層的系統架構，且指令緩衝區及資料緩衝區具可擴展性。我們針對不同的應用程式及不同大小的緩衝區做實驗，找出具有最佳效能的組合。此外，我們也提出了一個可管理內部緩衝區的方法稱為—Smart page replacement policy。利用此方法，可大幅降低處理器對資料記憶體的需求，減少資料做不必要的搬移。根據我們的實驗結果，處理器對資料記憶體的需求，大約可降為原本的百分之五十，以提升系統效能。
在DSP子系統中，加入了追蹤除錯單元可有效地幫助整個系統的除錯。我們提出的追蹤除錯單元可以很容易的嵌入DSP子系統中，可追蹤程式執行的過程、暫存器的變化及重要的內部訊號，幫助軟硬體在發展中快速的除錯。我們提供各種可觸發追蹤除錯的條件，並且可動態地做重新設定。因此，使用者可以專注於他們感興趣部分。此外，我們提出具有高壓縮率的方法稱為—Advanced packet compression method，這個方法可以使得壓縮率達到百分之二十六，以及提供更詳細的追蹤資訊。
我們建構了一個FPGA模型在多媒體驗證平台(UMVP2000)上，並且可成功的展示MP3、H.264等應用程式。根據我們建構的DSP子系統及所提出的除錯架構，可有效的減輕在嵌入式數位訊號處理器或者微處理器的除錯過程中所遇到的挑戰。

In my thesis, we present a scalable DSP (Digital Signal Processor) subsystem and its debugging infrastructure framework. Our proposed framework has been ported to a low-power embedded DSP core, called Starfish, developed by National Tsing-Hua University and National Chiao-Tung University.
The Starfish subsystem integrates the Starfish core with memory management unit, instruction buffer, data buffer, and our trace/debug unit (TDU). The memory subsystem is a two-level architecture to reduce the overhead of the data transfer on the bus. With our scalable memory subsystem, we can evaluate the performance of the entire DSP system rapidly. A large variety of combinations of instruction/data buffers are experimented to obtain the optimized parameters with targeted applications. In addition, we also present a smart page replacement policy to manage these internal buffers. With this mechanism, the page request of the data memory will be manipulated efficiently. As compared with the original straightforward implementation, about a 50 percentage reduction of the data memory access can be achieved by using our approach.
Furthermore, our DSP subsystem also integrates a effective TDU to help the system debugging. Our TDU can be easily embedded in the DSP subsystem to help trace the program flow, register change, also customized internal signals. Locating and analysis the hardware/software bugs will become easy accordingly. The trace/debug conditions of our TDU are highly reconfigurable. Various trigging conditions with predefined program range can be configured dynamically. Therefore, the user is able to focus on the interested region. In addition, we proposed an advanced packet compression method to compress the trace information with a higher compression rate. The proposed approach achieves about up to 26 percentage data compression ratio with lot more detailed trace information.
An FPGA prototype has been constructed by using the multimedia verification platform, UMVP2000, to successfully demonstrate the targeted applications such as MP3 and H.264, with the help of the Starfish core design team, and the application development team. With the proposed DSP subsystem, the development and debugging challenges of the embedded DSP or microprocessor can be alleviated effectively.

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