以介面破裂成長之預測法研究微電子元件之可靠度

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研究生：	李昌駿 Chang-Chun Lee
論文名稱：	以介面破裂成長之預測法研究微電子元件之可靠度 Investigation of Micro Electronic Devices Reliability Using Interfacial Crack Growth Prediction Methodology
指導教授：	江國寧 Kuo-Ning Chiang
口試委員:
學位類別：	博士 Doctor
系所名稱：	工學院 - 動力機械工程學系 Department of Power Mechanical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	179
中文關鍵詞：	可靠度、介面破裂、J積分、有限單元分析、能量釋放率、束縛/鬆放之破裂預測、銅導線/低介電係數、介電層連接、封裝、敏感度分析、反應曲面法
外文關鍵詞：	Reliability, Interfacial crack, J-integral, FEA, Energy release rate, Tie-release crack prediction, Cu/low-k interconnects, Package, Sensitivity analysis, RSM
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為了降低相鄰線路間所產生之高RC延遲效應，以大馬士革（Damascene）製程技術發展之多層堆疊結構型態的銅導線/低介電係數（Cu/low-k）材料系統，業已被採用作為下一世代積體電路（IC）晶片之導線連接系統。而此材料系統於滿足半導體電子元件之縮減元件尺度，與持續提升其操作性能等需求的同時，為一獲取電子訊號高速度傳遞之有效且急迫的解決方案。然而，接合材料間之熱膨脹係數（CTE）與彈性係數的不匹配。且，Low-k材料多具低破裂韌度（Fracture Toughness）與低接合黏著力之材料特性。因此，銅導線/低介電係數內導線連接系統在半導體前段晶圓與後段封裝製程之溫度負載的導入後，發生接合介面之破裂成長的可能性大幅增加。此破裂成長現象亦可見於其它電子元件諸如先進封裝結構內之焊點破壞。綜合以上所述，破裂失效情形已成為主要的熱電與力學耦合之可靠度問題，且亟待相關領域之研究者解決。
鑑於破裂失效問題對於元件可靠度之影響日益重要，本研究發展一基於有限單元計算之束縛/鬆放新式破裂預測方法，用以研究電子元件內之接合材料於介面破裂成長過程中，破裂應力對於元件可靠度影響之衝擊。再者，系統性地建立一以計算模擬為基底且結合統計分析方法之設計流程，採用敏感度分析與反應曲面法（RSM）研究顯著設計參數對於目標反應影響之程度。藉此，新式元件之力學可靠度於設計發展初期即可掌握與提升，並具減少需要試驗次數之優點。當使用本研究提出之新式破裂預測方法時，穩定破裂能量之估算，可藉由J積分方法，於裂縫尖端周圍配合適當地積分路徑與足夠有限單元網格之使用，以獲得一固定值。研究結果指出一矩形圍繞積分路徑將可得到穩定之材料介面裂縫破裂能量。而進行上述模擬分析時亦應遵守下列幾點重要規則：(a)裂縫尖端位置須置放於J積分路徑圍繞區域之中心點，且矩形路徑之長邊應與破裂波傳方向平行；(b)矩形路徑之深寬比（短邊/長邊）建議需小於0.1；(c) 於跨過接合材料介面之圍繞路徑短邊方向上，以破裂面為分隔點之各側材料至少需包含三層有限單元以減少數值計算之誤差。此外，利用四點彎矩試驗之有限單元分析與多層low-k介電薄膜的相關實驗結果之比較，驗證此J積分預測方法為可靠的。除了上述提及之基於能量法的破壞準則外，另一則可藉由模擬估算之介面破裂應力，配合已涵括考慮介面臨界應力的破壞準則，用以評估破裂發生之可能性。為了確保本研究提出之預測方法為正確且適切的，並揭露比較與傳統預測方法之差異，故選擇具Cu/low-k堆疊結構之PBGA封裝，以及DL-WLCSP晶圓級封裝結構作為破裂模擬分析之載具。研究分析之結果皆符合於相關實驗之結果。
由本研究之各項分析結果可知，針對於先進電子元件其破裂或脫層問題方面之力學可靠度所發展的預測方法，預期可廣泛地應用於各種元件結構。換言之，此基於破裂力學之新式破裂預測法，可應用於相異材料間之破裂發生、成長和延伸的預測；亦為本研究主要貢獻之處。

As the technology of the semiconductor process continues its scale miniaturization and improvement of electronic device performances, next-generation IC chips with Cu/low-k stacked structures and adopting the fabrication of a damascene module are being developed to meet the urgent requirements of reducing high RC delay so as to obtain high-speed signal communication. However, due to the mismatch in the CTE as well as a mismatch of elastic modulus existing in dissimilar materials, there is a high probability that doing so may contribute to interfacial cracks occurring or propagating within the multi-level interconnection system, composed of the copper interconnections and low-k materials, as a result of poor adhesion and intrinsically lower fracture toughness of the low-k materials when temperature loads are applied during the wafer level and the packaging level stages. Meanwhile, the phenomenon of crack growth is also observed in other devices such as the fracture of solder joints in advanced packaging structures. Therefore, this fracturing problem has become one of the critical issues for thermo-mechanical device reliability, which needs to be resolved urgently.
In this research, a novel tie-release crack prediction technique based on finite element calculation is developed to investigate the stress-induced impacts on the thermo-mechanical reliability of electronic interconnects during the whole cracking growth process of the bi-material interface. In addition, the entire processes of a simulation-based optimal design combined with statistics techniques are systemically constructed to study the impacts of the significant design parameters on the concerned response by using the sensitivity analysis and sequential RSM methodologies. Thus, the mechanical reliability of the new device will not only be greatly enhanced at the initial design stage, but the technique will also reduce the amount of required tests. On the other hand, when utilizing the proposed tie-release crack prediction technique through the use of a suitable integral contour path with sufficient finite element meshes adjacent to the crack tip, the cracking energy, which determines the opportunity of crack advance, is estimated by the J-integral method to tend toward a stable value. All analytic results indicate that a rectangular integral path is suggested for obtaining a stable J-integral value. In addition, the following conditions must also be satisfied with the J-value estimation in a FEA: (a) the crack tip must be at the center of the contour path, and the long side of the abovementioned contour path must be parallel to the direction of the crack propagation, (b) the aspect ratio of the contour path coming from the short side divided by the long side should be less than 0.1, and (c) the short side of the contour path, as well as the direction of the film thickness should include at least three layers of elements in each side of the fracture surface. Moreover, by means of a 4-point bending test FEA model and a comparison with the relative experimental data of multi low-k dielectric films, the methodology of finding a stable J-integral value for dissimilar materials has been validated to be reliable. In addition to the failure criterion based on the energy method referred to above, the simulation of an interfacial fracture based on the critical interfacial stresses estimation that must be determined experimentally is also adopted to judge the occurrence of the crack. To ensure that the proposed prediction methodology is correct and feasible, both wafer-level and packaging level device structures such as a PBGA package with Cu/low-k stacked structures, as well as the DL-WLCSP, respectively, for the fracture issues are implemented as the test vehicles to demonstrate the difference from the traditional prediction techniques. All analytic results reveal a good agreement with the consequences of relative device tests.
Based on the above, the development of design/prediction methodologies for the cracking/delamination issues regarding the mechanical reliability of advanced electronic devices presented in this investigation can be demonstrated and widely applied in various device structures. In other words, both the feasibility and the correctness of the novel prediction crack techniques based on fracture mechanics for resolving the problem of the interfacial crack occurring, growing and extending, in dissimilar materials are the major contributions of this research.

ABSTRACT (CHINESE)    I
ABSTRACT    III
ACKNOWLEDGEMENT    V
TABLE OF CONTENTS    VI
LIST OF TABLES    IX
LIST OF FIGURES    X


CHAPTER  1  INTRODUCTION    1
1.1 Motivation of Research    1
1.2 Literature Survey    2
1.2.1 Development of Packaging Technologies and Packaging Reliability Issues    2
1.2.2 Variety and Designs of Advanced Packaging Structures    4
1.2.3 Review of Micro Joints Reliability    8
1.2.4 Development of the Nano/Micro Scaling Integrated Circuit Fabricated Process
and Its Subsequent Physical Failure Mechanism    11
1.2.5 Interfacial Adhesion Strength of Cu/Low-k Interconnects    14
1.2.6 Impact of Packaging Technologies on the Novel Chip with Stacked Cu/Low-k
Interconnects    15
1.2.7 Review Applications of the Finite Element Analysis for Calculating Fracture
Energy of Crack    17
1.3 Research Goal    19

CHAPTER  2  FUNDAMENTAL THEORIES    21
2.1 Theory of Computational Fracture Mechanics    21
2.1.1 Stress/Displacement Fields of Crack Tip and Energy Release Rate    21
2.1.2 Fracture Energy and Fracture Criteria    24
2.2 Theory of Interfacial Fracture Mechanics    25
2.2.1 Stress/Displacement Fields of Interfacial Crack Tip    25
2.2.2 Interfacial Fracture Energy and Fracture Criteria    27
2.3 Application of the J-Integral Method for the Fracture    28
2.3.1 Fracture of the Elasto-Plastic Bulk Materials    28
2.3.2 Fracture Criteria of Dissimilar Materials    30
2.3.3 Interfacial Crack Prediction of Low-k Materials    32
2.4 Virtual Crack Closure Technique    33
2.5 Stress Analysis of Micro Structures Based on the Finite Element Method    38
2.6 Numerical Method and Convergence Criteria    40
2.7 Reliability Analysis of Micro Structures    42
2.7.1 Reliability Prediction of Electronic Packaging Structures    42
2.7.2 Statistical Analysis of the Reliability Experimental Data    44
2.8 Factorial Design and Response Surface Analysis    45
2.8.1 Factorial Design and Analysis of Variance    45
2.8.2 Application of Response Surface Methodology    47
2.8.3 Central Composite Design    49
2.8.4 Box-Behnken Design    50
2.8.5 Other Response Surface Designs    50

CHAPTER 3 SIMULATION-BASED DESIGNS AND THERMAL CYCLE
TESTING FOR ADVANCED PACKAGES    52
3.1 Finite Element Modeling for Wafer Level Package with Dummy Solder Joints    53
3.2 Analysis and Comparison between Finite Element Analysis and Accelerated Thermal
Cycle Testing    55
3.3 Sensitive Analysis with Advanced Simulation Model    56
3.4 Response Surface Modeling and Optimization Based on Finite Element Analysis    60
3.4.1 Construction of Regression Model    60
3.4.2 Validation of Accuracy    61

CHAPTER 4 PREDICTION METHODOLOGY OF INTERFACIAL CRACKS
USING THE J-INTEGRAL METHOD    64
4.1 Prediction Methodology of the Energy Release Rate for the Interface of Dissimilar
Materials    64
4.2 Finite Element Analyses and Experimental Verification for Cu/Low-k Interconnects    65
4.2.1 Procedures of the Finite Element Analysis for Packages with Stacked Cu/low-k
Dielectric Structure    65
4.2.2 Prediction Methodology Discussion for the Obtainment of a Reliable Energy
Release Rate of the Interfacial Crack    67
4.2.3 Effect of Finite Element Mesh Density Nearby a Crack Tip    68
4.2.4 Construction of the Finite Element Model for a 4-Point Bending Test    69
4.2.5 Prediction and Comparison for Fracture Toughness of Multi-Thin Films
between the Finite Element Analysis and Experimental Measurement    70
4.3 Predicted Results Compared by Different Methodologies    71
4.3.1 Comparison with the Analytical Solution    71
4.3.2 Comparison with Virtual Crack Closure Technique    74
4.4 Stability of the J-Integral Value for Various Types of Interfacial Crack    74
4.5 Geometrical Impacts of the Analytic Structure on the J-Integral Value    77
4.6 Discussion of the Stability of the J-Integral Value Integrated with the Application
of the Sub-Modeling Technique    79

CHAPTER 5 FINITE ELEMENT TECHNIQUE OF TIE-RELEASE INTERFACIAL CRACK PREDICTION    88
5.1 Development of the Tie-Release Interfacial Crack Prediction Technique    88
5.2 Applications of the Tie-Release Interfacial Crack Prediction Technique    89
5.2.1 Interfacial Fracture of the Stacked Cu/low-k Structure    89
5.2.2 Solder Joint Failure of Wafer Level Package with Dummy Joints    92

CHAPTER 6 CONCLUSIONS AND RECOMMENDATIONS    99
6.1 Conclusions    99
6.2 Future Work and Recommendations    102

REFERENCES    104
TABLES    126
FIGURES    131

                                

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