研究生: |
張嘉祐 |
---|---|
論文名稱: |
針對半導體廠之酸槽爐管製程發展整合性派工法則以期望降低產品週期時間 An Integrated and Improved Dispatching Approach to Reduce Cycle Time of Wet Etch and Furnace Area in Semiconductor Fabrication |
指導教授: | 張國浩 |
口試委員: |
簡禎富
張國浩 陳文智 |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 英文 |
論文頁數: | 30 |
中文關鍵詞: | 排序 、排程 、派工法則 、批量 、模擬系統 |
外文關鍵詞: | Sequencing, Scheduling, Dispatching, Batch size, Simulation |
相關次數: | 點閱:2 下載:0 |
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查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在半導體產業中,酸槽與爐管製程具有許多的特徵與限制,例如:等候時間限制、酸槽順序性、爐管區負載平衡、批量大小考量…等等。在同時必須考慮這些複雜限制的情況下,如何發展一個有效率的整合性派工法則以達到績效指標水準為此製程非常重要的課題。本研究探討範圍為半導體廠之酸槽與爐管製程,並發展一個整合性的派工法則,同時考慮排序與排程的方法,期望降低此段製程之產品週期時間。我們提出的派工法則考慮多因子組合,將舊有方法與負載-剩餘等候時間比例法 (LR-ratio Method) 結合以決定最佳的批量加工順序與派到適當之加工機台。我們與一間國內知名半導體廠合作,透過數值實證研究分析,考慮所有重要的系統特徵並收集線上資料建立一個模擬系統,將廠內原有之派工法則與我們所發展的派工法則進行績效指標之比較,其結果發現產品平均週期時間改善幅度約為8%。
[1] S. S. PanWalker and W. W. Iskandar, "A survey of scheduling rules," Operation Research, Vol. 25, No. 1, pp. 45-61, 1977.
[2] Russ M. Dabbas and John W. Fowler, "A new scheduling approach using combined dispatching criteria in wafer fabs," IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 3, pp. 501-510, 2003.
[3] Glassey, C.R. and Weng, W.W., "Dynamic batching heuristic for simultaneous processing," IEEE Transactions on Semiconductor Manufacturing, 14(2), pp. 77-82, 1991.
[4] J.W. Fowler, D.T. Phillips, G.L. Hogg, "Real-time control of multiproduct bulk-service semiconductor manufacturing processes," IEEE Transactions on Semiconductor Manufacturing, 5 (2), pp. 158-163, 1992.
[5] Marcel F. Neuts, "A general class of bulk queues with Poisson input," The Annals of Mathematical Statistics, Vol. 38, No. 3, pp. 759-770, 1967.
[6] R.K. Deb, R.F. Serfozo, "Optimal control of batch service queues," Advances in Applied Probability, 5 (2), pp. 340-361, 1973.
[7] Elif Ak?al?, Reha Uzsoy, David G. Hiscock, Anne L. Moser, and Timothy J. Teyner, "Alternative loading and dispatching policies for furnace operations in semiconductor manufacturing: a comparison by simulation," Proceedings of the 32nd conference on Winter simulation, 2000.
[8] Weng, W.W. and Leachman, R.C., "An improved methodology for real-time production decisions at batchprocess Workstations," IEEE Transactions on Semiconductor Manufacturing, 6 (3), pp. 219-225, 1993.
[9] Yang, D. L., & Chern, M. S., "A two-machine
owshop scheduling problem with limited waiting time constraints," Computers and Industrial Engineering, 28 (1), pp. 63-70. 1995.
[10] Ling-Huey Su, "A hybrid two-stage flowshop with limited waiting time constraints," Computers and Industrial Engineering, 44, pp. 63-70, 2003
[11] Wolfgang Scholl and Joerg Domaschke, "Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations," IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 273-277, 2000.
[12] James T. Lin, Chien-Chi Tsai, Yin-Yann Chen, Tzu-Li Chen, "Dispatching
Rules with Queue-Time-Limit Consideration for Furnace inWafer Fabrication
Factory," Journal of Advanced Engineering, Vol. 4, No. 3, 273-278, 2009.