(無電阻)應用於無限通訊具偵測直流偏壓電路及自我校正迴路之可調增益放大器

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研究生：	李青澔 Ching-Hao Lee
論文名稱：	(無電阻)應用於無限通訊具偵測直流偏壓電路及自我校正迴路之可調增益放大器 A Resistorless Variable Gain Amplifier With DC Offset Measurement & Auto Calibration Loop For Wireless Communication
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	87
中文關鍵詞：	可變增益放大器
外文關鍵詞：	Variable Gain Amplifier
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這篇論文實現出一個無電阻並具有自動消除輸出直流偏移電壓的可變增益放大器。全部使用金屬半場效電晶體無利用任何電阻模組,減少使用的光罩如此可降低製成價錢。此外,可調整電阻網路改變增益。此放大器採用超級源級隨耦器的特性來當輸入級以致於可達到較高的線性度。在電阻網路方面,為了讓非線性的開關電阻線性化,在可變增益放大器內部增加了兩個共模增益迴路,穩定共模電壓提高整體線性度。除此之外,使用以數位電路為主的直流偏移電壓自我校正迴路來減少電路輸出的直流偏移電壓。

此設計採用台積電0.18 µm互補式金屬半導體氧化物製程並且面積總共佔。此可變增益放大器的增益範圍從-6 dB到56 dB，並以2 dB為一個增益間距。此電路操作在1.8 V的電源供應器下，偏壓電路加上三級可變增益放大器共消耗6.6 MA的電流。總諧波失真在輸入訊號頻率在1 MHz和固定輸出擺幅在，在最小增益時為-55.5dB,在最大增益的時為-62dB。絕對增益誤差小於0.2dB,相對增益誤差小於0.2dB。頻寬方面, 串接三級之後在最大增益時有20MHz。輸入三階點為18 dBV在0dB增益時。雜訊方面,在增益為最大時輸入雜訊為15.9 。在直流偏移電壓自我校正迴路中，所需要的校正時間小於5us。當輸入20 mV的直流輸入偏移電壓於最大增益時，輸出直流偏移電壓可在校正完之後小於100 mV。

This thesis describes a complementary metal oxide semiconductor (CMOS) Variable Gain Amplifier (VGA) with digitally controlled gain. Implemented in a standard 1.8V, 0.18 CMOS process, this VGA adopts the degeneration type amplifier to vary voltage gain and uses the super source follower input stage to enhance the linearity. Besides, instead of any resistor model, this VGA’s resistor network only uses transistor-level substitution in order to eliminate the non-linear effect of MOS switches and achieves high linearity. A comparator is used in measuring DC offset voltage, and digitally controlled calibration loop is applied to achieve the DC offset cancellation.

An experimental chip is fabricated in TSMC 0.18 µm CMOS process with total area of . The VGA provides -6~56 dB gain range with 2 dB step and more than 20 MHz bandwidth. The current consumption from a single 1.8 V power supply is less than 6.6mA. The total harmonic distortion (THD) is smaller than -55.5 dB at the minimum gain setting; smaller than -62dB at the maximum gain setting when input signal operates at a 1 MHz and less than output swing. The input third intercept point (IIP3) is 18 dBV at 0dB gain setting, and the input referred noise is 15.9 at maximum gain setting. The output DC offset is less than the 100mV when 20 mV input DC offset is applied under calibration operation with calibration time less than 5us.

Chapter 1  Introduction………………………………………...……..1
1  Motivation……………………………………………………….1
2  Receiver Architecture……………………………………………2
3  Thesis Organization……………………………………………...6

Chapter 2  The Basic Concepts of VGA…………………………...…8
1    VGA in AGC Loop……………………………………………...8
2    Basic VGA topology…………………………………………...13
3    VGA Specification……………………………………………..15
3.1    Linearity……………………………………………………………...16
3.2    Noise…………………………………………………………………21
3.3    Other Design Issue…………………………………………………...23
4    DC Offset Cancellation………………………………………...26

Chapter 3  VGA Circuit Realization………………………………...30
1    VGA Implementation………………………………………….31
1.1   The Traditional VGA Architecture…………………………………...32
1.2    The Proposed VGA Architecture…………………………………….38
1.3    The Improvement of Variable Resistor Network………………….....42
1.4    The Proposed VGA with Common Mode Feedback……………….. 46
1.5   Cascaded Three Stages……………………………………………….47
2    Unity Gain Buffer……………………………………………...50
3    Current Bias Circuit…………………………………………...51

Chapter 4  DC Offset Measurement & Auto Calibration Loop...…54
1    DC Offset Calibration Loop…………………………...…….54
2    Comparator…………………………………………………….59
3    Digital-to-Analog Converter…………………………………...61
4    Successive Approximation Register…………………...………62

Chapter 5  Layout and Simulation Results……………………...64
1    Layout………………………………………………………….64
2    Simulation Results………………….………………………….68
2.1  VGA Simulation Result. ……………………………………….69
2.2  Unity Gain Buffer Simulation Result…………………………….76
2.3  DAC (Digital to Analog Converter) Simulation Result…………….77
2.4  Comparator Simulation Result………………………………….78
2.1  Current Bias Simulation Result……………………………...….79
3    Summary…………………………………………………..80

Chapter 6  Conclusions & Future Works…………………………...85

                                

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