OCT(Optical Coherence Tomography)是一種新的醫療式影像產品，主要是利用光學的干涉原理來成像，和其他的醫療器材相比，擁有不帶輻射影響和不需要注射顯影器的優點，在掃描過後對人體沒有任何的副作用，主要應用在表面組織和器官的檢測。目前分為TD、FD兩種系統，本篇論文根據其中的FD OCT系統架構，以硬體的方式實現訊號處理跟影像處理的部份，並且將其整合成單一的成像晶片，以提高整體系統的成像速度為目標，整個晶片共分成四個單元，分別是訊號處理的Resample Unit、Hamming Window、FFT，和影像處理的Log Unit。Resample Unit目的在校正影像的輸出形狀，把扇形的資料利用內差法重新取樣成方便觀察的矩形形狀，並且利用四組記憶體的交互使用，達到接受資料不中斷的目的，Hamming Window則負責把相鄰的line data變成互相有週期關係，減少最後成像line跟line之間不連續的情況，FFT參考了Oh和Lim的演算法推導和硬體設計架構，使用Radix-2^4和Radix-2^3為基底來拆解DFT，在硬體架構上選擇了throughput rate很高的Pipeline架構，並且使用了CSD乘法器代替了Radix-2^3和Radix-2^4裡面的複數乘法器，有效的降低了面積的使用。影像處理的Log運算，以自然對數為底和使用泰勒展開式進行化簡，為了節省面積，將部份泰勒展開式的結果捨去，在不影響SQNR太大的情況下來設計硬體電路。透過TSMC 0.18-um的電路合成，在Slow Model下可以達到80MHz之操作頻率，面積505.92K的邏輯閘可以達到80 M pixel/sec之輸出率。

OCT(Optical Coherence Tomography) is a type of medical imaging products, and has the advantage of no effects of radiation and injection Developer, no side effects on the human body, and mainly used in the detection of surface. This system has two types: TD(Time Domain) and FD(Frequency Domain). In this thesis, FD OCT system architecture is applied to design the hardware circuit, and toward the goal of raise frame rate. The chip is dividing into signal processing part and image processing part, using the Resample Unit, Hamming Window, FFT and other signal processing units, which are Log Unit for image processing, Resample Unit aimed at correcting the shape of the image output, interpolation method to resample sector data became the rectangular shape, and two memories to achieve high throughput rate purposes. Hamming Window is responsible for that the adjacent line data becomes a cycle of mutual relations, reducing the final imaging line with the line between the discontinuity. The proposed FFT(Fast Fourier Transform) processor refers Oh and Lim's algorithm derivation and hardware design architecture and uses Radix-2^4 and Radix-2^3 as the basic units to disassemble DFT(Discrete Fourier Transform),and the high throughput rate Pipeline hardware architecture is selected with the use of CSD(Canonic Signed Digit) multipliers instead of the complex multiplier to effectively reduce the area. Log image processes operations to the natural logarithm of the bottom, and a Taylor expansion is applied for simplification. In order to save space, without affecting the SQNR to design circuits. The proposed FFT processor is synthesized by a TSMC 0.18-μm process under the Slow Model of 80 MHz operating frequency with gate count of, 505.92K logic gates and can reach the output rate of 80 M pixel /sec.

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