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研究生: 鄭湘蕙
Jheng, Siang-Huei
論文名稱: 免除參考電壓及具錯誤容忍技術的電荷分享式連續漸近式類比數位轉換器
A Reference-free Charge-Sharing SAR ADC with Error Tolerance Technique
指導教授: 黃柏鈞
Huang, Po-Chiun
口試委員: 謝志成
謝秉璇
林宗賢
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 103
語文別: 中文
論文頁數: 79
中文關鍵詞: 類比數位轉換器電荷域電荷變動偏移量錯誤容忍機制
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  • 由已知的研究顯示,深腦電刺激可以抑制帕金森氏症患者的病情,但是腦內運作的機制仍然未知,故欲發展一個可以無線傳輸電源的微系統,來達到研究的目的。而為了使前端感測到的生醫訊號做更進一步的資料處理,需要透過類比數位轉換器,來將感測到的訊號轉換成數位碼,以利後端數位訊號處理操作。此微系統在無線傳輸的過程中,需要將二次測線圈的載波訊號轉換成內部晶片的直流電源,但以此無線傳能方式會造成較大的漣漪(Ripple)抖動,而造成類比數位轉換器效能低落。
    考量到電源抖動造成類比數位轉換器效能低落的問題,本論文提出一個可以免除參考電壓的連續漸近式類比數位轉換器。透過內部自行產生參考電壓,不需外接抖動電源,可使類比數位轉換器保有原來設計的性能表現。同時利用錯誤容忍機制,可補償比較器上,因為製程變異而造成電荷變動偏移。使用0.18μm標準CMOS製程,量測結果顯示,此類比數位轉換器可以操作在免除參考電壓的情況下,在0.75V~1V仍然可以操作保持SNDR為46.7dB。而在1V的情況下,取樣頻率可以由167KHz到7.7MHz。在VDD上若有一個250mV振幅的抖動時,相較於傳統的類比數位轉換器SNDR大降至剩下29dB,此類比數位轉換器仍可保持SNDR有44.25dB。故由結果顯示,在電源有較大抖動情況下,利用免除參考電壓的方式,此類比數位轉換器仍可以保持穩定性能。


    摘要 I Abstract II 目錄 III 圖目錄 V 表目錄 IX 第一章 簡介 1 1.1研究背景 1 1.2研究動機 5 1.3章節介紹 6 第二章 類比數位轉換器架構選擇 7 2.1類比數位轉換器規格 7 2.2類比數位轉換器架構 13 2.3連續漸近式類比數位轉換器架構 14 第三章 提出的連續漸近式類比數位轉換器架構 23 3.1免除參考電壓理念 23 3.2錯誤容忍機制 26 3.3提出的SAR ADC子電路 33 3.3.1取樣保持電路 33 3.3.2比較器 37 3.3.3數位控制器 39 3.3.4電壓提升電路 43 3.3.5數位類比轉換器 44 3.4整體模擬結果 47 3.4.1佈局圖 47 3.4.2佈局後模擬結果 49 第四章 晶片量測 52 4.1量測結果 53 4.2規格比較表 63 4.3模擬和量測討論 64 4.4效能比較表 73 第五章 結論和未來研究方向 74 5.1結論 74 5.2未來研究方向 76 參考文獻 77

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