目前由IEEE 802.15.3c 工作小組制定的無線個人網路(WPAN)標準，其目標為提供每秒數十億bit(multi-Gbps)的資料率，以滿足下一世代短距離且超高速通訊技術之需求。於此標準中所定義的高速介面(HSI)模式採用正交分頻多工(ODFM)技術，其擁有極佳的頻寬使用效率以及對抗非理想通道的能力，而在諸多調變方式中被視為熱門選擇。在以正交分頻多工為基礎的通訊系統中，快速傅立葉轉換器為其關鍵模組。針對無線個人網路的應用，如何設計一個擁有長點數、高輸出率，與合理硬體成本的快速傅立葉轉換處理器，便是個極為重要的課題。
　　在本論文中，我們提出一個擁有高輸出率且高硬體效率的2048 點快速傅立葉/反傅立葉轉換處理器，其中平行路徑的數目從四條延伸至八條。同時，一個有效率的記憶體存取方式以及以常數乘法為基礎之乘法單元也被提出，以減少平行路徑數目加倍所帶來的功率與面積消耗。再者，一個新的多資料進位(Multi-data scaling)方法也在本論文中被提出，藉由簡單的控制單元，可輕易的與多路徑延遲回授(Multiple delay-feedback)架構結合。我們使用UMC 90-nm 1P9M 製程實現所提出的處理器，其面積為1.18 mm2，且在300MHz 的操作頻率下消耗功率為127 mW。與先前四條平行路徑的架構相比，我們的處理器只有多出21.6%的面積，並且在高達2.4G sample/s 的輸出率下，其功率消耗只多了8.5%。此外，一個128 點的快速傅立葉轉換處理器也經由UMC 90-nm 1P9M 製程完成晶片製作，以驗證我們所提出架構的高輸出率與高硬體效率。此晶片之面積為0.53mm2，於52MHz 操作頻率其功率消耗為6.8 mW，且最高可提供2.08G sample/s 的輸出率。因此，我們提出的2048 點快速傅立葉/反傅立葉轉換處理器，針對未來以正交分頻多工為基礎的無線個人區域網路系統之實現，是一個極佳的解決方案。

Wireless personal area network (WPAN), currently under development by IEEE 802.15.3c Task Group, targets to provide multi-giga bits per second (multi-Gbps) data rate for the short-distance and ultra-high speed communication technology in the next generation. The high-speed interface (HSI) mode defined in this standard adopts orthogonal frequency division multiplexing (OFDM), which, with great bandwidth efficiency and invulnerability to non-ideal channel, is regarded as a prospective modulation strategy. Its specifications, however, impose a great challenge on the design of its key component, a long-length and high-throughput-rate Fast Fourier Transform (FFT) processor with acceptable hardware cost.
In this thesis, we proposed a high throughput-rate and hardware-efficient 2048-point FFT/IFFT processor, in which the number of parallel paths is extended from four to eight.
Besides, an efficient memory-accessing scheme and a novel constant-based multiplier unit are also proposed to reduce both area and power consumptions resulted from doubled data-path numbers. Also, a new multi-data scaling method is proposed, which can be easily integrated with multi-path delay-feedback (MDF) architecture using relatively simple control logic. The proposed FFT/IFFT processor is implemented in UMC 90-nm 1P9M process, whose core area is 1.18 mm2 and power consumption is 127 mW at 300MHz operating frequency. Compared with previous four-path architecture, the proposed processor has only 21.6% more area cost and provides up to 2.4G sample/s throughput rate at only 8.5% more power consumption. Moreover, a test chip of 128-point FFT processor is fabricated using UMC 90-nm 1P9M process to verify the high throughput-rate and hardware-efficiency of our architecture. This test chip has a core area of 0.53 mm2, a power consumption of 6.8 mW at 52 MHz operating frequency, and a maximum throughput rate of 2.08G sample/s. Therefore, the proposed 2048-point FFT/IFFT processor is a promising solution to the realization of OFDM-based WPAN systems in the future.

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