MB-OFDM UWB Viterbi解碼器設計及晶片實現｜國立清華大學博碩士論文庫

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研究生：	蔡佩玲 Pei-Ling Tsai
論文名稱：	MB-OFDM UWB Viterbi解碼器設計及晶片實現 Modified Viterbi Decoder and Chip Implementations for MB-OFDM UWB
指導教授：	吳仁銘 Jen-Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	74
中文關鍵詞：	維特比解碼器、超寬頻
外文關鍵詞：	Viterbi
相關次數：	點閱：2 下載：0
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超寬頻無線通訊系統最大的特色就是可以使用超大頻寬3.1-10.6GHz來傳送資料，美國聯邦通訊委員會( Federal Communications Commission)在2002年2月14日批准了超寬頻系統的商業化，將來可預期在消費性電子產品的市場上會有很大的發展。由於使用低功率的傳送訊號，超寬頻無線通訊系統即使因為可使用的頻寬大，而使傳送訊號與其他通訊系統相衝突，也不會因此而干擾到其他通訊系統，或是使傳送訊號受到嚴重干擾。IEEE 802.15.3a目前有兩種超寬頻無線通訊系統的標準，分別是多頻帶正交分頻多工(Orthogonal Frequency Division Multiplexing ,OFDM) 和直接序列 ( Direct Sequence ,DS)兩種技術，本篇論文架構與設計將以多頻帶正交分頻多工 (MB-OFDM) 技術為主。
通訊系統中使用通道編碼可大幅提升傳送資料的正確性，超寬頻無線通訊系統中所制定的通道編碼的編碼比率，也就是未經編碼前資料的長度與經過編碼後的資料長度比是1/3，但是為了提供較快速的傳送速度，可使用截去技術產生不同的編碼比率，但糾錯能力也會相對的下降。在目前通用的解碼器中，維特比解碼器 (Viterbi decoder)效果較佳，且硬體複雜度也較低，一般也建議使用此解碼器，而維特比解碼器也正是超寬頻無線通訊系統所預定使用的通道解碼器。
在這篇論文中為了能達到超寬頻無線通訊系統的高速傳輸速率，我們將針對維特比解碼器做更深一步的研究，改變其運作架構以得到更有效率的解碼方式，最後我們將此設計架構以晶片實現。

Ultra-Wideband (UWB) is a technology for transmitting information spread over a large bandwidth. FCC (Federal Communications Commission) authorizes the unlicensed use of UWB in 3.1–10.6 GHz. Due to extremely low emission levels, UWB system tends to be short-range and indoors without huge signal interference to other communication systems. There are two techniques specified by IEEE 802.15.3a for Ultra Wideband system. In this thesis, the proposed UWB system employs orthogonal frequency division multiplexing.
Viterbi Decoder is the channel decoder used for UWB system. To decrease the bit error rate with a noisy channel, channel encoding and decoding are used to protect the transmitted data bits. Viterbi Decoder is one of the decoders for convolutional encoder, and also the specified decoder for MB-UWB system.
For ultra-wideband (UWB) communication systems, high-speed Viterbi Decoder is sufficient for its high data rates. In this thesis, multiple architecture systems, acquisition method, sliding block, and parallel method, are proposed for high-speed propose.

Contents

Contents…………………………………………………………………………...i
List of Figures…………………………………………………………………..iv
List of Tables……………………………………………………………………vi
Abstract…………………………………………………………………………..viii

Chapter 1 Introduction………………………………………………………...1
Chapter 2 Foundation of Error Correcting Coding………….............3
2.1    Introduction……………………………………………………………....3
2.2    Channel Codes…………………………………………....................4
    2.2.1 Introduction……………….……………………………………….....4
    2.2.2 Block codes and convolutional codes……………..………………….5
2.3    Convolutional Codes…………...............................................................6
    2.3.1 Introduction……………….……………………………………….....6
    2.3.2 Basic structure…………….……………………………………….....7
    2.3.3 Generator sequences……….………………………………………....9
    2.3.4 Trellis diagram…………….……………………………………........10
2.4    Viterbi Decoding…………......................................................................12
    2.4.1 Introduction…………….……………………………………............12
    2.4.2 Maximum likelihood decoding and metrics………………………....13
    2.4.3 Basic decoding steps…...….………………………………………...14
         2.4.3.1 Decoding steps…………………………………….………..14
2.4.3.2 An example of decoding………………………….………..16
    2.4.4 Implementation issues…….………………………………………...21
2.5    Punctured Convolutional Codes.........................................................25
Chapter 3 Overview of MB-OFDM UWB Baseband System.....27
3.1    Introduction………………………….…………………………………..27
3.2    Overview of OFDM…………………..…….…………………………28
    3.2.1 OFDM Introduction…….……………………………………….......28
    3.2.2 Basic OFDM Transmitter and Receiver….………………………....29
3.3    Multi-band OFDM PLCP sublayer .…….………………………….30
    3.3.1 Rate-dependent parameters…….………………………………......31
    3.3.2 Timing-related parameters.……………………………………........31
    3.3.3 Data scrambler………….………………………………………......32
    3.3.4 Convolutional encoder…….……………………………………......33
    3.3.5 Bit interleaving…….……………………………………………......36
    3.3.6 Constellation mapping….………………………………………......38
3.3.6.1 QPSK…………………………………………….………..39
3.3.6.2 Dual-carrier modulation (DCM)………………….………..40
Chapter 4 Modified Viterbi Decoder Architecture…..…………..…43
4.1    Introduction……………………………………….…………………......43
4.2    Decoder Architecture…………………………………..…………........44
        4.2.1 The acquisition method……………………………………………...44
        4.2.2 Sliding Block………………………………………………………...46
        4.2.3 Parallel architecture……………………………………………….....49
4.3    Implementation Issues……………………….………..………….........51
        4.3.1 Timing usage…………………………………..………………….....51
        4.3.2 Soft decision……………………………………………..………......52
        4.3.3 Best state estimate……………………………………………….......53
4.4    Block Diagram of Hardware Implementation.…….…………........54
Chapter 5 Simulation Results……………………………………………...56
5.1    Simulation Results…………………………….……………..................56
        5.1.1 Simulation platform..……………………………………..……….....56
        5.1.2 Simulation results for full system………………………..………......57
        5.1.3 The throughput and conclusion of simulation results……………….61
        5.1.4 RTL Simulation for Viterbi Decoder……………………..……….....64
5.2    Chip Design for Viterbi Decoder….……………………………..….64
        5.2.1 I/O signals………………………………………………..……….....64
        5.2.2 Design flow……………………………………………..……….......66
        5.2.3 DRC and LVS report……………………………………..……….....66
        5.2.4 Chip specification list……………….…………………..………......69
        5.2.5 Chip layout view….……………………………………..………......70
5.3    Comparison….……………………………..……………………………73
Chapter 6 Conclusion and Future Work………………………………..74

                                

[1] Jun Tang and Keshab K. Parhi , “Viterbi Decoder for high-speed Ultra-Wideband communication systems ”.
[2] Herbert Dawid, Gerhard Fettweis, and Heinrich Meyr, “A CMOS IC for Gb/s Viterbi Decoding: System Design and VLSI Implementation”, IEEE Transactions on very large scale integration (VLSI) systems.
[3] Peter J. Black, and Teresa H.-Y. Meng, “A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder”, IEEE Journal of solid-state circus.
[4] Zhongjun Wang Wenzhen Li Lee Guek Yeo Yanxin Yan Yujing Ting Masayuki Tomisawa , “A Technique for Demapping Dual Carrier Modulated UWB OFDM Signals with Improved Performance”.
[5] Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, and Chen-Yi Lee, “Design of a Power-Resuction Viterbi Decoder for WLAN Applications”.
[6] Jun Jin Kong, and Keshab K. Parhi, “Low-Latency Architectures for High-Throughput Rate Viterbi Decoders”.
[7] Jung-Gi Baek, Sang-Hun Yoon, Jong-Wha Chong, “Memory Efficient pipelined Viterbi Decoder with Look-Ahead Trace Back”.
[8] Jan-Sun Han, Tae-Jin Kim, Chanho Lee, “High Performance Viterbi Decoder Using Modified Register Exchange Methods”.
[9]”Multiband OFDM physical layer specification”
[10] F. Sun and T. Zhang, “Low-power State Parallel Relaxed Adaptive Viterbi Decoder,” IEEE Trans. Circuits and Syst. I, vol. 54, no. 5, pp. 1060-1068, May 2007/8/21
[11] M. Anders, S. Mathew, R. Krishnamurthy, and S. Borker, “A 64-state 2GH 500Mbps 40mW Viterbi Accelerator in 90nm CMOS,” in Sympo. VLSI Circuits Dig. Tech. Papers, 2004, pp. 174-175.
[12] M. Anders, S. Mathew, S. Hsu, R. Krishnamurthy, and S. Borker, “A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS,” in IEEE Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 256-257.
[13]Dah-Jia Lin, and Chen-Yi Lee, “A Low-power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length”

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