隨著元件製造技術微縮至深次微米尺寸，高摻雜離子植入(high dose implant)便成為元件特性參數調整中不可或缺的重要應用。然而在高摻雜離子植入製程的光阻去除步驟中，如何有效地去除光阻殘留一直是整個製程中的個關鍵。為了有效率並完全地除去光阻殘留，以四氟化碳(CF4)氣體為主的電漿去光阻製程一直被廣泛應用在高摻雜離子植入製程的光阻去除步驟裡。然而四氟化碳電漿中的氟原子卻也容易穿透過多晶矽閘極而侵入閘極氧化層並使元件的特性參數發生變化。在本研究中，應用了不同的四氟化碳電漿製程時間來得到不同的氟原子侵入程度藉以評估其對元件特性與可靠度所造成的影響。實驗結果顯示較長的四氟化碳電漿製程時間將造成氧化層的增加並引起臨界電壓上升。而四氟化碳電漿所引致生成的正電性氧化層捕捉電荷(oxide trapped charge)則會起平帶電壓負向平移。另外，由於氟原子會取代二氧化矽與矽介面之間原有矽-氫鍵結中的氫原子而變成鍵結能較強的矽-氟鍵結，因此其抗熱載子劣化能力與臨界電壓穩定性均會提高。但由於四氟化碳電漿會造成氧化層缺陷(defect)，故元件的氧化層崩潰電壓與氧化層崩潰電荷會降低。這樣的氧化層品質劣化現象以能提供較多氟原子穿透路徑的指插狀多晶矽上電極結構最為明顯。

As the device geometry continues to scale to deep sub-micron, high dose implant is essential in the source/drain for device optimization. However, in photoresist strip step of high dose implant process, carbonized photoresist residue becomes a critical issue. To effectively and completely remove any residue photoresist, a fluorine-based gas such as CF4 was widely used in photoresist ashing applications. A non-optimized CF4 ashing recipe would cause fluorine penetration into the gate oxide and affect device characteristics. In this work, different CF4 plasma process times were used in the source/drain photoresist strip process and the fluorine atoms were introduced into the polysilicon gate. The experimental result showed that longer CF4 plasma process time gave rise to additional gate oxide thickness and higher threshold voltage. Negative shift of flatband voltage were also found due to positive oxide trapping charge by CF4 plasma. A robust Si-F bond at the interface of SiO2/Si formed by CF4 plasma instead of original Si-H bond led to good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). But lower voltage-to-breakdown (Vbd) and charge-to-breakdown (Qbd) were also observed. This gate oxide integrity (GOI) degradation was triggered by the CF4 plasma-induced oxide trapped defects and happened especially in finger-type poly-Si gate test pattern which provided more exposed grain boundary for fluorine penetration than bulk–type one.

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