本論文使用TSMC 0.35-μm CMOS 2P4M標準製程實現一高速低功率消耗連續時間三角積分調變器(CTSDM)，它可以應用於需要寬頻中解析度與低功率消耗的無線通訊、照相或數位影像方面的應用。連續時間三角積分調變器包涵了一個由電阻電容式積分器所組成的三階迴路濾波器、四位元電流切換式數位類比轉換器與操作於每秒兩億次取樣頻率的四位元快閃式類比數位轉換器；藉由改良型Z轉換對應離散與連續時間之間的參數，來完成迴路濾波器雜訊轉移函數設計，我們使用取樣週期的一半來做額外回授路徑時間延遲的補償，同時設計一個負回授路徑與四位元的控制電路避免額外回授路徑時間延遲造成系統穩定度下降。整個連續時間三角積分調變器在10倍超取樣率下可以達到10-MHz的輸入頻寬，同時擁有65.5-dB的動態範圍與64.5-dB的訊號雜訊諧波比或10.5-bit的有效位元數，整體電路操作在3-V電壓源下功率消耗僅20.2-mW，且晶片面積為1.4X1.1-mm2。

A high-speed and low-power continuous-time sigma-delta modulator(CTSDM) is implemented in standard TSMC 0.35-μm CMOS 2P4M technology. The CTSDM is targeted for applications which demand wide-bandwidth, medium-resolution and low-power such as wireless communication, imaging or digital video. The CTSDM comprises a third-order RC-integrator loop filter, a 4-bit current steering digital-to-
analog converter, and a 4-bit flash analog-to-digital converter operating at 200-MHz clock frequency. The noise-shaping design is determined using modified Z-transform between discrete-time and continuous-time coefficients of the loop filter transfer function. The excess loop delay is set to half sampling period and the degradation of modulator stability due to excess loop delay is avoided with a negative path feedback and 4-bit trimming circuit. The CTSDM achieves 65.5-dB DR, and a 64.5-dB SNDR or 10.5 ENOB over a 10-MHz input bandwidth at 10 times oversampling rate. The total power consumption is only 20.2-mW from the 3-V power supply, and the core area is 1.4X1.1-mm^2.

[1] A.Rusu, D. R. L. González, and M. Ismail, “Reconfigurable ADCs Enable Smart Radios for 4G Wireless Connectivity,“ IEEE Circuits Devices Mag., vol. 22, No. 3, pp. 6-11, May-June 2006
[2] K. Honda, M. Furuta, and S. Kawahito, “A low-power low-voltage 10-bit 100-Msample/s pipeline A/D converter using capacitance coupling techniques,” IEEE J. Solid-State Circuits, vol. 42, No. 4, pp. 757-765, Apr. 2007
[3] J. Arias , L. Quintanilla, L. Enrı’quez, J. Herna’ndez-Mangas, J. Vicente, and J. Segundo “A 1-GHz, multibit, continuous-time, delta–sigma ADC for Gigabit Ethernet,” Elsevier Journal of Microelectronics, Vol. 39, No. 12, pp. 1642-1648, Dec. 2008
[4] A. Das, R. Hezar, R. Bryd, G. Gomez, and B. Haroun, “A 4th-order 86dB CT ΔΣ ADC with two amplifiers in 90mm CMOS,” ISSCC Dig. Tech. Papers, pp. 496-497, Feb 2005
[5] Y. Shu, B. Song, and K. Bacrania, “A 65nm CMOS CT ΔΣ modulator with 81dB DR and 8MHz BW auto-tuned by pulse injection,” ISSCC Dig. Tech. Papers, pp. 500-501, Feb. 2008
[6] W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun and D. Ribner, "A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD," IEEE ISSCC, Dig. Tech. Papers, pp. 438-631, Feb. 2008
[7] R. H. M. van Veldhoven, R. Rutten, and L. J. Breems, “An Inverter-Based Hybrid ΣΔ Modulator,” ISSCC Dig. Tech. Papers, pp. 493-494, Feb. 2008

[8] B. Putter, “A 5th-Order CT/DT Multi-Mode ΔΣ Modulator,” IEEE ISSCC Dig. Tech. Papers, pp. 244–245, Feb. 2007
[9] K. Chen, and T. Lee, “Design of a 320-MHz Continuous-Time Delta-Sigma Modulator with 5-MHz Signal Bandwidth,” Master`s thesis, NTU, 2009
[10] R. del R o, F. Medeiro, B. Perez-Verdu, and Á. Rodriguez-Vazquez, CMOS cascade sigma delta modulators for sensors and telecom error analysis andpractical design. Springer 2006
[11] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations. New York, NY: Springer, 2005
[12] F. Gerfers, K. M. Soh, M. Ortmanns, and Y. Manoli, “Figure of merit based design strategy for low-power continuous-time ΣΔ modulators,” Proc. IEEE Int. Symp. Circuits Syst. vol.4, pp. 233–236, Agu. 2002
[13] D. A. Johns and K. Martin, Analog Integrated Circuit Design, 1st ed. NY: Wiley, 1997
[14] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Wiley&Sons, Hoboken, 2005
[15] K. C.-H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Trans. Circuits Syst., vol. 37, pp. 309-318, Mar. 1990
[16] S. Patón, A. D. Giandomenico, and L. Hernández, “A 70-mW 300-MHz CMOS Continuous-Time ΣΔ ADC with 15-MHz Bandwidth and 11 Bits of Resolution,” IEEE J. Solid-State Circuits Vol. 39, No. 7, pp. 1056-1063, July 2004.

[17] S. Yan and E. Sánchez-Sinencio, “A Continuous-Time ΣΔ with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, Vol. 39, No. 1, pp. 75-86, Jan. 2004.
[18] W. Liu, and L. Dung, “On Analysis of Continuous-Time Sigma-Delta ADC with Practical Considerations,” Master`s thesis, NCTU, 2006
[19] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, Vol. 39, No. 7, pp. 1148-1158, Jan. 2004.
[20] N. H. E.Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Boston, MA: Pearson Education, Inc., 2005
[21] A. V. Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 315-324, Mar. 2001
[22] National Semiconductor, LM117/LM317A/LM317 3-Terminal Adjustable Regulator Data Sheet, National Semiconductor, 1997
[23] National Chip Implementation Center Web Site, http://www.cic.org.tw/cic_v13/
[24] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS Continuous-Time ADC With 20-MHz Signal Bandwidth 80-dB Dynamic Range and 12-bit ENOB,” IEEE J. Solid-State Circuits, Vol. 41, No. 12, pp. 2641-2649, Dec. 2006.
[25] Z. Li and T. S. Fiez, “A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, Vol. 42, No. 9, pp. 1873-1883, Sep. 2007.