研究生: |
鍾豐旭 Chung, Feng-Hsu |
---|---|
論文名稱: |
一個十億到一百億赫茲寬頻鎖相迴路 A 1-10 GHz Wide Tuning Range Phase Locked Loop |
指導教授: |
朱大舜
Chu, Ta-Shun |
口試委員: |
吳仁銘
王毓駒 朱大舜 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 65 |
中文關鍵詞: | 鎖相迴路 、壓控震盪器 、電感 、可程式除頻器 、相位/頻率偵測器 、電荷幫浦 |
外文關鍵詞: | Phase-Locked Loop, Voltage-Controlled Oscillator, Inductor, Programmable Divider, Phase/Frequency Detector, Charge Pump |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在多數的通訊系統中需要一個本地震盪訊號源作為訊號解調之用,而不同的頻段對應到各種不同的應用,在本論文中提出一個可調頻率範圍為1-10GHz的切換式LC交錯耦合振盪器架構並將其整合於鎖相迴路,預期可以產生出涵蓋L頻段(1~2GHz)、S頻段(2~4GHz)、C頻段(4~8GHz) 、以及X頻段(8~12GHz)的訊號源,根據需求而提供所需的訊號頻率。
論文的第一部分介紹關於寬頻可調範圍震盪器的相關文獻與其架構,由於單一可變電容的可調範圍有限,一基本架構的LC共振腔其可調的頻率範圍也會受限,因此有許多文獻提出各種不同的振盪器以及共振腔架構使其輸出頻率範圍加寬,以及介紹能夠產生雙頻段訊號的共振腔,使得單一振盪器可以有多種應用。
論文的第二部分介紹提出的振盪器架構,使用的架構為多模式切換以達成寬頻輸出的效果,並將會介紹使用的串聯電感架構與工作原理,預期的頻率輸出範圍為1-10GHz;而除頻器的部分則是以串接九級的除二除三單元來達到可除100~1000的寬頻除數範圍,最後再介紹使用的相位頻率偵測器以及電荷泵架構,相位頻率偵測器為傳統的NAND邏輯閘架構;而電荷泵則是採用Current Steering架構;迴路濾波器將以外接在PCB板上面的方式來進行實際量測。
論文的第三部分為各子電路以及鎖相迴路閉迴路的模擬結果,電感的部分使用IE3D電磁模擬軟體來作電感的佈局以及模擬,再使用ADS模擬軟體等效被動元件的電路模型,電路模擬方面則使用Cadence來模擬以及做整個電路的佈局,使用的製程為台積電65奈米製程,操作電壓為1.2V,最後則是根據本次電路設計做個簡單的總結。
A 1-10GHz Wide Tuning Range Phase Locked Loop is proposed in this thesis.
In the first part, previous architectures of wide tuning range VCOs are introduced. The tuning range of single varactor is limited, so the frequency tuning range of basic LC-VCO is also limited. Consequently, various wideband VCOs are implemented to increase the frequency tuning range.
In the second part the architecture of 1-10GHz Wide Tuning Range VCO is proposed, the expected output frequency is 1-10GHz. The divider is implemented by series of 2/3 cells to achieve the wide division range of 64~1023. Finally the architectures of phase frequency detector and charge pump are introduced.
The simulation results are included in the third part, the used process is TSMC 65 nm CMOS technology with 1.2V supply voltage.
[1] 高曜煌, “射頻鎖相迴路IC設計, ” 滄海書局, 2005.
[2] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proc. IEEE Custom Integr. Circuits Conf, May 1998, pp. 555–558.
[3] Y. Seong-Mo and K. K. O, “Switched resonators and their applications in a dual-band monolithic CMOS LC-tuned VCO,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 1, pp. 1705–1711, Jan. 2006.
[4] M. Demirkan, S. P. Bruss, and R. R. Spencer, “11.8 GHz CMOS VCO with 62% tuning range using switched coupled inductors,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig. Papers, Jun. 2007, pp. 401–404.
[5] L. Geynet, E. De Foucauld, P. Vincent, and G. Jacquemod, “Fully-integrated multistandard VCOs with switched LC tank and power controlled by body voltage in 130 nm CMOS/SOI,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig. Papers, Jun. 2006, pp. 129–132.
[6] M. Kossel et al., “LC PLL with 1.2-Octave locking range based on mutual-inductance switching in 45-nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 436–449, Feb. 2009.
[7] J. Steinkamp, F. Henkel, and P. Waldow, “Multimode wideband 130 nm CMOS WLAN and GSM/UMTS,” in Proc. IEEE Int. Workshop on Radio-Frequency Integr. Technol., Dec. 2005, pp. 105–108.
[8] A. Goel and H. Hashemi, “Frequency switching in dual-resonance oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 571–582, Mar. 2007.
[9] Z. Safarian and H. Hashemi, “Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors,” IEEE Transactions On Circuits And Systems, vol. 56, no. 8, pp. 1830–1843, Aug. 2009.
[10] A. Karl, F. Behbahabni, and A. A. Abidi, “RF-CMOS Oscillators with Switched Tuning,” in Proc. of the IEEE Custom Integrated Circuits Conf., May 1998, pp. 555-558.
[11] C.S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegli, and Z. Wang, “A Low-power Truly-modular 1.8GHz Programmable Divider in Standard CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039- 1045, July 2000.
[12] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J . Solid-State Circuits, vol. 24, no. 2, pp. 62-70, 1989.
[13] S. B. Sleiman, J. G. Atallah, S. Rodriguez, A. Rusu, and M. Ismail, “Wide-Division-Range High-Speed Fully Programmable Frequency Divider,” IEEEWorkshop on Circuits and Systems and TSISA conf., pp.17-20, June 2008
[14] R. Nonis, E. Palumbo, P. Palestri, and L. Selmi, “A design methodology for MOS current-mode logic frequency dividers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 245–254, Feb. 2007.
[15] Won-Hyo Lee, Jun-Dong Cho, Sung-Dae Lees, “A High Speed and Low Power Phase-Frequency Detector and Charge-pump ” Proceedings of the ASP-DAC '99. Asia and South Pacific on Design Automation Conference, 18-21 Jan. 1999.
[16] I. Young, J. Greason, and K. Wong, “A PLL clock generator with 5 to l l0 MHz of lock range for microprocessors, ” IEEE J. Solid-State Circuits, vol. 27, no 11, pp. 1599-1607, Nov. 1992.
[17] W. Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” 1999 IEEE International Symposium on Circuits and Systems, ISCAS'99. vol. 2, pp. 545-548, July 1999.
[18] J. Lee, M. Keel, S. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronics Letters, vol. 36, no. 23, pp. 1907-1908, Nov. 2000.
[19] 楊渝澤, “應用於矽製程的去嵌入技術、電感及接觸墊研究,” 國立中央大學電機工程研究所碩士論文, 2004.