高介電層閘極金氧半電晶體電應力產生之界面陷阱與氧化層電荷分佈量測研究

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研究生：	呂君章 Chun-Chang Lu
論文名稱：	高介電層閘極金氧半電晶體電應力產生之界面陷阱與氧化層電荷分佈量測研究 Detection of stress-induced Interface Traps and Border Traps in MOSFETs with High-K Gate Dielectrics
指導教授：	張廖貴術 Kuei-Shu Chang-Liao
口試委員:
學位類別：	碩士 Master
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	89
中文關鍵詞：	高介電係數、電荷汲引、可靠性
外文關鍵詞：	high-k, charge pumping, reliability
相關次數：	點閱：1 下載：0
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為了滿足ITRS元件持續縮小化的要求，一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題，然而在材料替換的過程中，許多問題產生，如電荷捕獲(charge trapping)，臨界電壓(threshold voltage)飄移，載子遷移率(mobility)下降等，因此應用在高介電係數閘極介電層電晶體的界面缺陷(interface traps)及氧化層缺陷(oxide traps)可靠度分析因應而生。
本論文主要的研究工作是將電荷汲引技術應用在元件的可靠度分析上面，實驗結果顯示，高介電係數閘極介電層中的弱鍵結很容易因為電應力的影響而捕捉電荷，造成起始電壓漂移，而介電層中的缺陷可能是不固定的缺陷，行為類似電洞。
此外，本篇中也討論了電荷汲引電流中的漏電流成分解決方法，以及改變閘極信號振幅的影響。
最後深入的探討量測縱深分不實的重要參數：限制因子。藉由適當的調整閘極信號偏壓高低，可以選擇電子或電洞作為量測時的限制因子。

Abstract
To fulfill the scaling scenario as projected in the International Technology Roadmap for Semiconductors (ITRS), it is widely believed that a high-k (high permittivity) dielectric is needed to replace SiO2 as the CMOS gate dielectric to reduce significantly the gate leakage current. With the using of these alternative materials, the analyses of interface and gate dielectric quality have become important due to the higher interface states and worse gate dielectric quality. The interface states can trap electrons or holes and even the border traps can also. Trapped charge causes instabilities of electrical properties like threshold voltage shift, carrier mobility degradation and less reliability. Hence, the studies of the interface states and depth profile of border traps and trapping mechanism play a significant role in the new generation semiconductor industry.
In this work, we applied charge pumping technique to reliability measurement. Experimental results indicate that the weak bonds present in high-k gate dielectric are easily trapped by charges after stress; thus, stress results in a large Vth shift. It is also demonstrated from the Nbt profile that the border trap induced by stress is probably not a fixed trapping center but a mobile defect like hole.
Moreover, we discuss the tunneling component of CP current and effects of voltage swing in high-k gated MOSFETs. An effective method was proposed to eliminate the tunneling component.
Finally, the limitation factor of Nbt(x) depth profile measurement was investigated. We should carefully set voltage swing and bias level to choose electron or hole as limitation factor.

Contents
Abstract...................................................I
Contents.................................................III
Table of Figure Contents..................................V

Chapter 1  Introduction_______________________________________________1
1 Motivation.............................................1
2 Effective mobility extraction..........................2
2.1 Why is mobility important?……………………………2
2.2 Traditional measurement…………………………………3
2.3 Split capacitance-voltage (C-V) technique…………3
3 Powerful measurement technique:.......................4
3.1 Developments of Charge Pumping technique…………4
3.2 Energy distribution of interface-trap density in MOSFETs with high-k gate dielectric………………………………5
3.3 Depth profile of border traps in MOSFETs with high-k gate dielectric.....................................6

Chapter 2    Introduction of charge pumping technique _______15
1 Introduction and motivation..........................15
2 Energy distribution of interface trap density in high-k gated MOSFETs...........................................16
2.1 Basic charge pumping technique...................16
2.2 Interface trap energy distribution Dit(E) in high-k gated MOSFETs...........................................17
3 Detection of border traps in MOSFETs with high-k gate dielectric................................................19
4 Conclusions...........................................21

Chapter 3  Reliability measurement of MOSFETs with high-k gate dielectric by CP depth profile technique ____________34
1 Detection of trap generation in MOSFETs with high-k gate dielectric...........................................35
2 Charge migration of trap in high-k gate dielectric of MOS device................................................36
3 Reliability measurement of devices from industry.....40
4 Conclusions..........................................42

Chapter 4  Effects of leakage current, gate pulse amplitude, electron/hole limitation on charge pumping technique _______________________________________________56
1 Research motivation...................................56
2 Tunneling component of CP current in high-k gated MOSFETs...................................................57
3 Effects of gate voltage swing on CP measurement.......60
4 Filling function variation of SiO2 and HfO2...........62
5 Limitation factor of CP measurement on high-k MOS devices...................................................67
6 Conclusions...........................................70

Chapter 5  Conclusions and future works __________________85
1 Conclusions.........................................85
2 Suggestions and future works........................87

Reference ________________________________________________88

                                

Reference

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