研究生: |
陳哲偉 Chen, Che-Wei |
---|---|
論文名稱: |
製作鋁/氧化鑭/金奈米晶體/二氧化矽/p型矽快閃記憶體 Fabrication of Al/LaxO1-x/Gold Nanocrystal/SiO2/p-Si Flash Memory |
指導教授: |
葉鳳生
Yeh, Fon-Shan |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 107 |
中文關鍵詞: | 金奈米晶體 、浸鍍法 、高介電材料 |
外文關鍵詞: | gold nanocrystal, immersion plating, high-k material |
相關次數: | 點閱:3 下載:0 |
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本實驗提出一種簡單、低成本且高產量的浸鍍法(immersion plating)製作金奈米晶體(gold nanocrystal),並完成金氧半電容(MOSC)結構的非揮發記憶體。在沉積金奈米晶體後快速熱退火為了改善金粒與矽的介面。以氧化鑭當作控制介電層,藉以提升寫入/抹除速度,
利用高溫氧化法在矽上成長二氧化矽當作穿遂氧化層,厚度為5、7奈米,接著低壓沉積非晶矽,厚度為2奈米,此層作為浸鍍法行氧化還原反應時矽原子的來源,浸鍍液成分為四氯化金酸/氫氟酸濃度為0.48mM/1.5mM,浸鍍時間3秒鐘,金奈米晶體於矽表面還原形成,以掃描式電子顯微鏡和穿透式電子顯微鏡觀察金粒尺寸及密度。
對於控制介電層,氧化鑭厚度20、30奈米由電子槍蒸鍍後回火400度時間10分鐘,蒸鍍鋁後,形成鋁/氧化鑭/金奈米晶體/二氧化矽/p型矽結構,氧化鑭(20奈米)配合二氧化矽(7奈米)和氧化鑭(30奈米)配合二氧化矽(5奈米),由電容-電壓量測來決定寫入抹除特性。為了改善慢的抹除速度,沉積金奈米晶體後快速熱退火200度30分鐘,由電流-電壓的特性,討論穿遂電流機制,發現在小電場(0~8MV/cm)時主要為直接穿遂,大電場(9~13MV/cm)時為F-N穿遂主導,發現穿遂電流有明顯提升,RTA製程改善寫入抹除速度。氧化鑭(30奈米)/二氧化矽(5奈米)此厚度條件下,在104秒後仍有1.1伏的retention特性,在103次寫入抹除週期後仍有2.1伏的endurance特性。
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