隨著通訊技術的進步，利用網際網路或其他通訊設備來交換資料已深植在我們生活的每一個角落。網路資料的處理已成為電腦系統裡所需解決的問題，這一方面在過去是由一般的CPU來處理，而現在已發展成由專門的網路處理器(NPU)來提供高速的封包處理，以解決現今日亦嚴重的網路流量問題。網路與通訊安全在過去僅用於政府機關、軍事單位或私人機構，如今也隨著網際網路的發達而成為今後急需解決的問題，因此資訊加密的處理也跟著網路資料傳輸一樣，將會有越來越多的需求。
在此篇論文中， 我們提出了一個具前瞻性的密碼處理器來加速一般CPU或網路處理器對加密資料的處理。由於加密演算法種類繁多，本設計採取模組化(core-based)的設計，將選定的加密演算法如AES、RSA、HMAC及RNG 加以實現為IP，並提出一個可調整的硬體架構將所有的IP整合成為一個密碼處理器。
在AES演算法部分，我們提出了一個高效能低成本的電路設計方式，主要是採取Composite Field Arithmetic運算來實現演算法的核心Sbox部分，相對於查表(table-lookup)的設計方法，可節省較多的面積。對於加解密過程中所要用金鑰，我們也提出了一種可同步計算金鑰的電路，而不需使用額外的記憶體來儲存金鑰。基於對AES處理器的經驗，我們也實現了一個可調變的AES處理器，經由對AES演算法之參數的調整，可產生新的AES演算法，藉以進一步的提高系統的安全性。在我們提出的架構中可以利用較合理的面積來達到以上的要求，並可快速的做調變。其他如RSA、HMAC及RNG線路的實現則是由實驗室其他成員所貢獻。
密碼處理器中所有的IP皆遵守AMBA AHB Slave傳輸協定，並使用AMBA AHB作為On-Chip Bus，我們設計了一個具有Descriptor-based DMA功能的模組來控制IP的運作，並自動完成資料的輸入與輸出。DMA中可程式化的channel與密碼處理器中的加密引擎是可以隨效能的需求而增減。整個處理器的測試方面，則是採用實驗室內部所開發完成的STEAC系統，來整合各個模組的測試方法，及產生相應的測試電路。
最後在本篇論文中，我們對於模組化設計方式(core-based design methodology)在測試整合方面遇到的測試排程問題提出了一個解決方法，利用圖學理論的分析，我們的方法可以同時考慮各模組的測試相容性、測試通道的分配，來產生接近理想值的測試排程，同時也考慮到測試功率的問題。這個方法也在ITC’02 benchmark中表現出不錯的結果，並可以用來解決我們密碼處理器的測試整合問題上。

With the rapid advance in communication technology, the use of networks and communication
facilities for transmitting information between people, companies or countries has been implanted
deeply in our real life. Network processing becomes an emerging problem that needs to be dealt
with in the computer system. The ability to properly serve heavy traffic on internet through network
equipments is now provided by a fast network processing chip. The security of communications,
originally a problem of government, military or privileged organizations, becomes one of
the major concerns among individuals and corporations. There is an increasing demand in network
processing, including the security processing.

This thesis describes the development of an advanced cryptographic processor (an analogous term
is security processor, which is also used in the rest of the thesis). As a coprocessor of a CPU
or a network processor (NPU), the cryptographic processor reduces the load of the host by providing
the computing power of security processing. Due to the heterogeneous characteristic in
cryptographic functions, our design is based on the core-based design methodology. The cryptographic
functions have been specified first and implemented with crypto-engines. Base on these
basic building blocks, a scalable architecture is provided to integrate these crypto-engines into a
cryptographic processor.

First, cryptographic functions such as AES, RSA, HMAC algorithms and Random Number Generation
are selected to be the algorithms that our cryptographic processor supports. We propose a
high-throughput low-cost AES processor design. The S-Box of the AES algorithm is implemented
based on the composite field arithmetic. The area overhead can be greatly reduced compared with
the table look-up method. The key expansion procedure is implemented by the proposed on-the-fly
key generation hardware, which further removes the need of on-chip memory. This cost-effective
implementationwill be used as a crypto-engine for our cryptographic processor later. Other cryptoengines,
such as RSA, HMAC and RNG are contributed by oother members in our research group. Based on the experience on AES implementation, we also proposed a configurable AES processor
for extended security requirement. The parameters within the round function of AES algorithm can
be reconfigured on-line to become an extended AES cipher. Our architecture has relatively low area
overhead and rapid reconfiguration capability. When embedded in a communication system, the
security level can be further enhanced.
In the second phase, each crypto-engine is wrapped with an AHB slave interface. With the help of
an on-chip AHB, we develop a descriptor-based DMA module to integrate all the crypto-engines.
The DMA-like interface makes our cryptographic processor capable of loading the data automatically,
to be processed by specified crypto-engines, and transferring the result back to the system
memory. The host processor only needs to generate proper descriptors for it. In our architecture,
the number of channels in the DMA interface and the number of internal crypto-engines can be
easily configured to fit in different systems. The SOC Test Aid Console (STEAC) is also employed
to ease the test integration problem in our design.
Finally, we propose a graph-based method to solve the power-constrained test scheduling problem,
which is an important issue among test integration. The relationship between the test schedule
of a core-based design and the test access mechanism (TAM) design is investigated by our graph
model. We present a heuristic algorithm that can effectively assign TAM wire to each core, given
the test order. With the help of tabu search and graph model, the proposed algorithm allows rapid
exploration of the solution space. Experimental result for ITC02 benchmarks show that short
test length is achieved within reasonable computing time. This method can also solve the test
scheduling problem of our cryptographic processor.

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