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研究生: 顏文偉
論文名稱: 環形時間數位轉換器用於氣電倍增偵檢器
Two Ring Time-to-Digital Converter for Gas Electron Multiplier Detector
指導教授: 周懷樸
口試委員: 盧志文
范倫達
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 56
中文關鍵詞: 時間數位轉換器環形震盪器氣電倍增偵檢器陣列式氣體偵檢器
外文關鍵詞: Time-to-digital convertor, GEM detector
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  • 近年來,陣列式的氣電倍增偵檢器被用來量測來自宇宙輻射的X光偏振現象成為天文物理學中的重要課題。初期將使用現場可編輯邏輯閘陣列來完成此項多通道陣列式的氣電倍增偵檢器的建置。能量訊號由高度時間轉換器轉換後送入時間數位轉換器來辨別;位置訊號則直接使用時間數位轉換器判別。因此時間數位轉換器的好壞與否決定了氣電倍增偵檢器的解析度與精確度。本實驗內部的時間數位轉換器將使用環形時間數位轉換器為基礎,建置多通道陣列式的氣電倍增偵檢器。
    前置放大器由特殊應用積體電路來實現,而後端時間數位轉換器的處理使用現場可編輯邏輯閘陣列完成環形震盪器的電路架構。為了在單一一片現場可編輯邏輯閘陣列晶片上完成多通道陣列式的氣電倍增偵檢器,勢必引入誤差搜尋裝置或是時脈輸入緩衝器來做為輸入,以解決環形時間數位轉換器外部輸入的問題,因此晶片資源的利用也由於多通道的設計變得相當的重要,而計數器的數量將成為減少資源利用的一項重要指標。
    系統將如同特殊應用積體電路一般,以硬體描述語言進行設計,建置完成之現場可編輯邏輯閘陣列的氣電倍增偵檢器將會以通用匯流排送入個人電腦,作初步測試與分析。時間數位轉換器的波形測試結果有良好的線性度,該系統也由於使用現場可編輯邏輯閘陣列來完成,系統參數上的靈活度與方便性非常的良好,隨時可以進行調整。


    In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector for the present project has multi-signal channels. The TDC units are built using the FPGA on-board chips based on a Two-ring oscillator algorithm. The timing signals and the energy signals are fed to the time-to-digital converter (TDC) units and Amplitude-to-Time Converter (ATC) units respectively. Therefore, the resolution of TDCs is a very important parameter for the present application.
    The front-end units are implemented using an application-specific integrated circuit (ASIC) design. The data acquisition unit is implemented using commercial field programmable gate array (FPGA) circuits. The TDC unit using the FPGA logic gates is based on a Two-ring oscillator algorithm. For multi-channel GEM detector, there is not enough clock input port at a FPGA chip. As a result, an error finder unit or dedicated input clock buffer(IBUFG) is used and the number of counter has to be decreased to save the resource of FPGA.
    The FPGA configuration is designed using a hardware description language (HDL), similar to that used for the front-end ASIC. The TDC units, and the communication and control logics among channels are integrated using the built-in features of the FPGA board. The FPGA based system is then linked to a personal computer for data analysis. The control signal from the computer and the data communication are using USB port. Measurements using simulated signals have been performed. Results indicated that the FPGA-based TDC waveform has a good linearity and indicated that the system is very flexible for measuring parameter adjustments under various experimental conditions.

    摘要 i Abstract ii 致謝 iv 目錄 vi 表目錄 viii 圖目錄 ix 第 一 章 緒論 1 1.1 氣電倍增偵檢器讀出電路 1 1.2 研究動機與目的 3 1.3 研究大綱 4 第 二 章 文獻回顧 5 2.1 氣電倍增偵檢器與結構 5 2.2 氣電倍增讀出電路位置辨別原理 8 2.3 現場可編輯邏輯閘陣列 9 2.4 時間數位轉換器 12 2.4.1 游標尺延遲線時間數位轉換器 12 2.4.2 併波時間數位轉換器 15 2.4.3 雙環時間數位轉換器 16 2.4.4 雙環結構 16 2.4.5 環形震盪器 18 2.4.6 相位偵測器 19 2.4.7 多通道雙環時間數位轉換器 21 2.5 超高速積體電路硬體描述語言 23 第 三 章 系統設計原理與架構 27 3.1 理論說明 27 3.2 計數器縮減設計 28 3.3 引入誤差搜尋裝置架構 29 3.4 使用設備簡介 30 3.5 量測方法 33 第 四 章 量測結果分析 34 4.1 雙環時間數位轉換器電路功能波形分析 34 4.2 佔用資源 39 4.3 雙環時間數位轉換器解析度 42 第 五 章 結論與建議 44 參考文獻 46 第 六 章 附錄 48 附錄一: 48 附錄二: 52

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