研究生: |
林聖淳 |
---|---|
論文名稱: |
含矽穿孔及微接點三維晶片堆疊電子構裝可靠度分析 Reliability Analysis of Three Dimensional Chip Stacking Electronic Packaging with Through Silicon Vias and Micro-bump Interconnects |
指導教授: |
陳文華
鄭仙志 |
口試委員: |
林見昌
劉德騏 |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 動力機械工程學系 Department of Power Mechanical Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 64 |
中文關鍵詞: | 含矽穿孔及微接點三維晶片堆疊電子構裝 、三維晶片堆疊電子構裝可靠度分析 |
相關次數: | 點閱:3 下載:0 |
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近年來消費者對產品的輕薄化及高效能的需求,進行系統晶片整合以縮小構裝尺寸乃必然趨勢。然而,無論是同質或異質整合的系統構裝模組都會導致高功率密度,造成局部高溫甚至熱點。由於堆疊晶片模組中各元件之熱膨脹係數不匹配,易造成高度局部應力及構裝體破壞,故熱負載下的可靠度要求已成為先進構裝之重要課題之一。本論文即在發展一簡化、有效之有限單元分析模型,以探討含矽穿孔及微接點三維晶片堆疊構裝於加速熱循環負載下之可靠度。因微接點間距與尺寸均遠小於傳統構裝,且矽穿孔與矽晶片間存在嚴重熱膨脹係數不匹配,其熱負載之可靠度尤應予關注。
由於矽穿孔及微接點數量龐大,本論文首先利用有限單元法及Schapery計算公式對含矽穿孔單晶片進行等效熱膨脹係數分析,探討矽穿孔間距、直徑、二氧化矽層厚度及晶片厚度等因子對等效熱膨脹係數的影響。接著,以上述等效熱膨脹係數分析結果為基礎,本論文以工研院之含矽穿孔三維晶片堆疊構裝為載具,建立其三維全域精細、區域精細及全域/局部等三種有限單元結構分析模型,分別探討其於加速熱循環負載下之熱應力。與全域精細有限單元模型分析結果相比較,以有限單元法得到之等效熱膨脹係數配合區域精細及全域/局部有限單元模型分析所得結果,區域精細有限單元模型於準確性方面較全域/局部有限單元模型高,但全域/局部有限單元模型分析準確性尚可接受,於計算時間上全域/局部有限單元模型卻大大少於區域精細有限單元模型,區域精細有限單元模型計算時間為全域精細有限單元模型分析之百分之七十,但全域/局部有限單元模型僅需百分之八。
最後,本論文以全域/局部有限單元模型進一步結合Coffin-Manson疲勞壽命方程式探討三維晶片堆疊構裝在加速熱循環負載下微接點之疲勞壽命,並對不同的填充底膠、介金屬材料厚度、矽穿孔材料、直徑、間距及晶片厚度等影響因子進行參數化分析,以建構評估矽穿孔熱應力及微接點疲勞壽命之參考準則。
參考文獻
1. Andersson, C. and Lai, Z.(2005): Comparison of isothermal mechanical fatigue properties of lead-free solder joints and bulk solders. Materials Science and Engineering A, vol. 394, pp. 20–27.
2. Boresi, P. B. and Chong, K. P. (2000): Elasticity in Engineering Mechanic. John Wiley& Sons, Inc., NY.
3. Bowles, D. E. and Tompkins, S. S.(1989): Predictions of coefficients of thermal expansion for unidirectional composites. Journal of Composite Materials , vol. 23, pp. 370–388.
4. Box, G. E. P.; Hunter, W. G. and Hunter, J. S.(1978): Statistics for experiments. John Wiley & Sons.
5. Cheng, E. J. and Shen, Y. L.(2012): Thermal expansion behavior of though-silicon-via structures in three-dimensional microelectronic packaging. Microelectronics Reliability, vol. 52, pp. 534–540.
6. Coffin, L. F.(1954): A study of the effects of cyclic thermal stresses on a ductile metal. ASME transactions, vol. 76, pp. 931–950.
7. Darveaux, R.; Banerji, K.; Mawer, A. and Dody, G.(1994): Reliability of Plastic Ball Grid Array Assembly in Ball Grid Array Technology. McGraw-Hill, New York, pp. 379–439.
8. Darrel, R. F.; Steven, N. B. and Harold, S. M.(1994): Mechanics of Solder Alloy Interconnects. Springer, Inc.
9. DeVor, R. E.; Chang, T. H. and Sutherland, J. W.(1992): Statistical Quality Design and Control-Contemporary Concepts and Methods. Prentice-Hall, Inc.
10. Ege, E. S. and Shen, Y. L.(2003): Thermomechanical response and stress analysis of copper interconnects. Jourmal of Electronic Material, Vol. 32, pp. 1000–1011.
11. Engelmaier, W.(1983): Fatigue Life of Leadless Chip Carrier Solder Joints during Power Cycling. IEEE Transaction Component, Package, Manufacture Technology, vol. 6, pp. 232–237.
12. Hsieh, M. C. and Lee, W.(2008): FEA Modeling and DOE Analysis for Design Optimization of 3D-WLP. Electronics Systemintegration Technology Conference, pp. 707–712.
13. Hsieh, M. C. and Yu, C. K.(2008): Thermo-Mechanical Simulations for 4-Layers Stacked IC Packages. IEEE Intermational Conference on Thermal, Mechanical and Multiphysics Simulations and Experiments in Micro-Electronics and Micro-Systens. pp. 254-260.
14. Iannuzzelli, R.(1991): Predicting Plated-Through-Hole Reliability in High Temperature Manufacturing Process. Electronic Components and Technology Conference, Atlanta, USA, May 11-16, pp. 410–421
15. JEDEC Solid State Technology Association. (2005): Temperature Cycling JEDS22-A104C, EIA/JEDEC, USA
16. Kanchanomai, C.; Yamamoto, S.; Miyashita Y.; Mutoh, Y. and McEvily, A. J. (2002): Low Cycle Fatigue Test for Solders Using non-contact Digital Image Measurement System. International Journal of Fatigue, vol. 24, pp. 57–67.
17. Manson, S. S.(1966): Thermal Stress and Low Cycle Fatigue. McGraw- Hill, Inc.
18. Myers, R. H. and Montgomery, D. C.(1995): Response surface methodology: process and product optimization using design experiments.John Wiley & Sons.
19. Ladani, L. J.(2010): Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits. Microelectron Engineering, pp. 208–217.
20. Lau, J. H.; Chan, Y. S. and Lee, S. W. R.(2010): Thermal-enhanced and cost-effective 3D IC integration with TSV (through-silicon-via) interposers for high-performance applications. In: Proceedings of the ASME 2010 international mechanical engineering congress & exposition, pp. 635–640.
21. Lee, W. W.; Nguyen, L. T. and Selvaduray, G. S.(2000): Solder Joint Fatigue Models: Review and Applicability to Chip Scale Packages. Microelectronics Reliability, vol. 40, pp. 231-244.
22. Limaye, P.; Vandevelde, B.; Labie, R.; Vandepitte, D. and Verlinden, B. (2008): Influence of Intermetallic Properties in Reliability of Lead-free Flip-Chip Solder Joints. Transactions on Advanced Packaging, vol. 31, No.1, pp. 51–57.
23. Ranganathan, N.; Prasad, K.; Balasubramanian, N. and Pey, K. L. (2008): A study of thermo-mechanical stress and its impact on through-silicon vias. Journal of Micromechanics and Microengineering, vol. 19, No. 7, pp. 1001–1014.
24. Ryu, S. K.; Lu, X. Z. and Im, J. H.(2011): Impact of Near-surface Thermal Stress on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects. IEEE Trantions on Device and Materials Reliability, pp. 35–43.
25. Sakuma, K.; Andry, P. S.; Dang, B.; Maria, J.; Tsang, C. K.; Patel, C.; Wright, S. L.; Webb, B.; Sprogis, E.; Kang, S. K.; Polastre, R.; Horton, R. and Knickerbocker, J. U.(2007): 3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections. Electronic Components and Technology Conference, pp. 627–632.
26. Schapery, R. A.(1968): Thermal expansion coefficients of composite materials based on energy principles. Journal of Composite Materials, vol. 2, No. 3, pp. 380–404.
27. Selvanayagam, C. S.; Lau, J. H.; Zhang, X.; Seah, S. K. W.; Vaidyanathan, K. and Chai, T. C.(2009): Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. IEEE Transaction Advanced Packaging, vol. 32, pp. 720–728.
28. Shen, Y. L.(1993): Stresses, deformation, and void nucleation in locally debonded metal interconnects. Journal of Applied Physics, vol. 84, pp. 5525–5530.
29. Shen, Y. L.(2008): On the elastic assumption for copper lines in interconnect stress modeling. IEEE Transaction on Device and Materials Reliability, vol. 8, pp. 600–607.
30. Son, H. Y.; Jung, G. J.; Lee, J. K.; Choi, J. Y. and Paik, K. W.(2007): Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chip on Organic Substrates for Fine Pitch Applications. Electronic Components and Technology Conference, pp. 864–871.
31. Srinivasa, R. V.; Kripesh, V.; Wook, Y. S.; David, W. and Tay, A. A. O. (2005): Bed of Nails: Fine Pitch Wafer-level Packaging Interconnects for High Performance Nano Devices. IEEE Electronic Packaging Technology Conference, pp. 658–663.
32. Takahashi, K.; Terao, H.; Tomita, Y.; Yamaji, Y.; Hoshino, M.; Sato, T.; Morifuji, T.; Sunohara, M. and Bonkohara, M.(2001): Current Status of Research and Development for Three-Dimensional Chip Stack Technology. Japanese Journal of Applied Physics, vol. 40, pp. 3032–3037.
33. Takahashi, K.; Umemoto, M.; Tanaka, N.; Tanida, K.; Nemoto, Y.; Tomita, Y.; Tago, M. and Bonkohara, M.(2003): Ultra-high-density Interconnection Technology of Three-dimensional Packaging. Microelectronics Reliability, vol. 43, pp. 1267–1279.
34. Takashi, K.; Takayuki, T. and Mitsutoshi, H.(2008): Silicon Interposer with TSVs (Through Silicon Vias) and Fine Multilayer Wiring. IEEE Electronic Components and Technology Conference, pp. 847–852.
35. Tanaka, N. T.; Sato, Y.; Morifuji, T.; Umemoto, M. and Takahashi, K. (2002): Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module. IEEE Electronic Components and Technology Conference, pp. 473–479.
36. Tanaka, N. Y.; Yamaji, T.; Sato, Y. and Takahashi, K.(2003): Guidelines for Structural and Material-System Design of a highly Reliable 3D Diestacked Module with Copper Through-Vias. IEEE Electronic Components and Technology Conference, pp. 597–602.
37. Tanida, K.; Umemoto, M.; Morifuji, T.; Kajiwara, R.; Ando, T.; Tomita, Y.; Tanaka, N. and Takahashi, K.(2003): Au Bump Interconnection in 20μm Pitch on 3D Chip Stacking Technology. Japanese Journal of Applied Physics, vol. 42, pp. 6390–6395
38. Tanida, K.; Umemoto, M.; Tanaka, N. and Takahashi, K.(2004): Micro Cu Bump Interconnection on 3D Chip Stacking Technology. Japanese Journal of Applied Physics, vol. 43, pp. 2264–2270.
39. Teo, J. W. and Sun, F. Y.(2008): Spalling Behavior of Interfacial Intermetallic Compounds in Pb-free Solder Joints Subjected to Temperature Cycling Loading. Acta Materialia, vol. 56, pp. 242–249.
40. Tsai, I. T.; Wu, I. B.; Yen, S. F. and Chuang, T. H.(2006): Mechanical Properties of Intermetallic Compounds on Lead-Free Solder by Moire’ Techniques. Journal of Electronic Material, vol. 35, No. 5, pp. 1059–1066.
41. Wolf, M. J.; Dretschkow, T.; Wunderle, B.; Jürgensen, N.; Engelmann, G.; Ehrmann, O.; Uhlig, A.; Michel, B. and Reichl, H.(2008): High Aspect Ratio TSV Copper Filling with Different Seed Layers. Electronic Components and Technology Conference, pp. 563 – 570.
42. Yeo, A.; Lee, C.; John, H. and Pang, L.(2004): Flip Chip Solder Joint Fatigue Analysis Using 2D and 3D FE Models. 5th. International Conference on Thermal and Mechanical Simulation and Experiments in Micro-electronics and Micro-Systems, EuroSimE, pp. 549–555.
43. Yu, A.; Kumar, A.; Ho, S. W.; Yin, H. W.; Lau, J. H.; Houe, K. C. and Siang, L. P.(2008): Development of Fine Pitch Solder Microbumps for 3D Chip Stacking. Electronics Packaging Technology Conference, pp. 387–392.
44.Yu, C. F.; Cheng, H. C.; Tsai, Y. M.; Lu, S. T. and Chen, W. H.(2011): Influence of IMC surface Geometry and Material Properties on Micro-bump Reliability of 3D Chip on Chip Interconnect Technology , the 6th IEEE International Conference on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT). pp. 210–213.