藉由關鍵路徑之間的線性結構進行路徑延遲錯誤疊合

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研究生：	薛培英 Pei-Ying Hsieh
論文名稱：	藉由關鍵路徑之間的線性結構進行路徑延遲錯誤疊合 Path Delay Fault Collapsing by Linear Structures of Critical Paths
指導教授：	劉靖家 Jing-Jia Liou
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	54
中文關鍵詞：	延遲測試、延遲錯誤、路徑延遲錯誤模型、線性組合、功能敏化性路徑
相關次數：	點閱：3 下載：0
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隨著快速超大型積體電路的發展，對於在高頻工作中的電路，任何一個細小的製程缺陷都可能引入不正確的延遲，導致它無法在給定的工作頻率下正常工作，因此確保電路時序特性正確性為目標的延遲測試變的愈來愈重要。而路徑延遲錯誤亦是其中相當重要的議題，並且已經吸引了許多研究投入此領域，因此有不少重要的結果也都被發表出來了。
在一個電路中的路徑會因為電路上的結構而使得彼此之間可能有相關性，因此，一條未知其延遲的路徑能夠由已經得知延遲的路徑來線性組合而成。換句話說一個電路中所有路徑的延遲可以利用一個路徑的少量子集合的延遲來線性組合而成來得到；而其中這個路徑集合我們便叫它為基底路徑集合。為了得到電路中最大的路徑延遲，我們必須知道所有路徑的延遲才行；而其方法除了可使用測試樣本來直接測量路徑延遲這個傳統的方式之外，我們還可以像上面所講的利用基底路徑集合的線性組合來計算出其它路徑的延遲。在這一篇論文中，我們參考了在[2]中的演算法來找出線性依靠於基底路徑集合的其它路徑，並藉由疊合一些重複且不必要的電路結構圖以及增加更多的可測試路徑到基底路徑集合中來改善這個演算法，因而可以找出更多的線性依靠路徑。並且藉由這個方法，我們也避免了在路徑延遲錯誤模型中必須面對太多路徑的問題。

Paths in a circuit are structurally related to each other. Therefore, under certain assumptions, an unknown path delay could be calculated as a linear combination of known path delays [1]. In other words the delays of all paths of a circuit could be showed as a linear combination of the delays of a small subset of paths called the basis path set [2]. To find the maximum path delay, it must know the delay of all paths, either by direct measurement or by calculation. This means that every path not directly measured by a test pattern must be equal to a linear combination of basis path set. In this thesis, we improve the algorithm of determining linearly dependent paths based on the one given [2]. We combine some same and redundant structures of a circuit graph and increase more testable paths to the basis path set. Then, we will get more linearly dependent paths. The experimental results for benchmark circuits are given.

Introduction 8

1 Delay Testing Background . . 8
2 Overview of Path Delay Fault Model . . 9
3 Path Delay Fault Classification . . 12
3.1 Single-Path Sensitizable Path Delay Faults . . 13
3.2 Robust Testable Path Delay Faults . . 13
3.3 Non-Robust Testable Path Delay Faults . . 14
3.4 Functional Sensitizable Path Delay Faults . . 15
3.5 Summary . . 16
4 The Problems of Testing FS Path Delay Faults . . 17
5 Organization of the Thesis . . 18

Basis Definitions and Overview of PreviousWork 19

1 Circuit Structure and Path Graph . . 19
2 Expressing Unknown Path Delays by Linear Combination
    of Known Path Delays . . 22
2.1 A Solution for FS Path . . 23
3 Bounding Circuit Delay . . 24
4 Determining a Testable Ordered Basis Path Set . . 25
5 Modify a New Graph to Determine Linearly Dependent
    Paths . . 27

The Improved Method for FS Paths by Linear Combination
  of Testable Paths 35

1 Combine the Same Edges in the New Graph . . 35
2 An Improvement by Adding Testable Basis Path Set . . 40

Experimental Results 43

1 The Experimental Results for All Paths . . 43
2 Verification . . 43
3 The Experimental Results for All FS Paths and Critical
    Paths . . 45

Conclusions and Future Work 51

1 Conclusions . . 51
2 Future Work . . 51

                                

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