在本篇論文中，我們研究數種DSP平行處理的方法將H.263實做在一個VLIW DSP處理器上，藉由數位信號處理器的強大計算功能來加速視訊壓縮的處理。用DSP來處理影像、視訊壓縮是相當合適的，因為這些壓縮程式包含許多向量的運算，而DSP的長處就是在處理這一類數值運算。H.263，是一適用於PSTN上的視訊壓縮演算法。在進行視訊壓縮時，H.263會先將一張張的影像切割成一個個的區塊，而後在再對這一個個的區塊做Motion Estimation，希望能藉由前一張影像找尋到相似的區塊，之後再用DCT和Quantization來對相減之後的剩餘值進行壓縮和編碼的動作，以上這些處理運用Software Pipeline、Loop Unrolling的DSP程式技巧。
開發DSP的應用程式可以採用C程式語言。因為DSP的平行編譯器設計較為複雜，因此藉由DSP編譯器－Code Composer所編譯出來的DSP執行碼，在執行效率上，比起用組合語言所編寫的DSP程式來的沒有效率。編寫DSP組合語言程式時需要考慮許多的情況，像是Function Unit的分配、暫存器的配置、組合語言指令延遲週期的問題、記憶體的擺放，都是在編寫組合語言程式時要注意的。在本篇論文中，我們對H.263這視訊壓縮演算法中幾個較佔處理時間的部分改寫，而改寫的方式則是用手寫DSP組合語言程式的方式將C程式碼改寫成組合語言程式碼。藉由這樣的改寫，一般來說，在處理週期上跟Code Composer所編譯出來的程式碼比較起來可以大幅減少許多。而本篇論文的目標則是將H.263視訊壓縮程式實做在一數位信號處理器上，並且讓這視訊壓縮程式能夠即時執行。

In this thesis, we study several parallel process techniques on generating effective DSP code for H.263 video codec. Due to the rapid development of powerful VLIW DSP chips currently, it is possible to accelerate the complex computation of H.263 so that it can generate the compressed video in real time. H.263 is a novel video compression standard in H.324, which is nominated for PSTN communication. H.263 is a block-based coding scheme, uses motion estimation to search the best match block in the reference frame and adopts DCT and quantization to remove the spatial redundancies. It is no surprising that those computations can gain a large degree of parallelism in DSP computation. We use several techniques such as software pipelining, loop unrolling, etc to gain the possible benefit of parallelism.
Nowadays, the developing environment of DSP code is getting better due to the progress of complier technology. We simply can write down the code in C and the object code will be generated through code composer automatically. However, in our experience, the efficiency of such DSP execute program is not good quality comparing to the handwritten assembly code because of the weak of parallelism. In this thesis, several computation-intensive procedures were carefully investigated, especially for the possibility of parallelism. Besides, lots of problems, such as allocating function units and registers, settling on delay slots, etc. are all important in generating DSP assembly code. From the experimental results, in general, the execution cycles of assembly code is more less than that generated by the code composer.

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