低功率消耗的系統晶片設計是越來越重要，功率估算隨著整體晶片的面積的增加造成模擬所花費的時間更為長久。在現有的功率估算軟體以利用邏輯閘層級居多，但是在此一層級要來估算系統晶片功率有所困難，因此會把估測層級推升至電子系統層級來估算，此一層級雖然有快速的功能與時序模擬的能力但是功率估測上就較為薄弱。因此在電子系統層級做功率估測需要各類型矽智財的功率模型，過去建立功率模型是透過機率統計的方式來去推論訊號變化對功率損耗的影響，此種方法較為複雜也要花費更多的時間來建立功率模型。
本篇論文主要提供了一個可快速且有效率的建立功率模型的方法。我們提供一套自動化的流程，此流程針對不同的矽智財電路擁有不同的模組化的策略。第一種，我們根據一些關鍵的訊號來區分矽智財操作的模式，以建立其功率模型，這方法適用於各種不同的電路。第二種，我們會針對處理器這類型的矽智財建立指令集層級和管線精確這兩種不同精細度的能量模型。我們將此方法應用於PAC-DSP核心處理器，建立出多層次的功率模型，並且與邏輯閘層級比較模擬結果。在使用一般型矽智財功率模組誤差約在10%，提升至管線層級的模型則誤差約在2.43%，而模擬速度與邏輯閘層級相比約可大幅的提升約780倍。

High-level power estimation often relies on different power models. The modeling procedure of IPs is usually complex and time-consuming. In this thesis, we use quick and effective methodologies to model various IPs. We have two modeling strategies for different IPs. Firstly, we use some key signals to classify the operation modes of IPs and create the power model, called General IP model. Secondly, we adopt the instruction-level and stage-accurate approaches to characterize processor energy model that is based on the realistic instruction type and program counter registers to establish an accurate model. The proposed methodology is applied on AES and PAC-DSP core to create versatile power models for performing the gate-level power estimation. The realistic application programs are used as training patterns due to its similarity to operating environment, and thus, the overhead of generating specific training patterns for each IPs is ignored. With general IP model, the estimate error of processor is about 10%, and the error could be reduced to only 2.43% by the stage-accurate model. Moreover, the speedup of our approach is 780X faster than gate-level simulation.

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