電路使用一段時間後，都會無法避免的產生老化的現象。從電晶體的角度來看，老化會影響到電晶體的負偏置溫度不穩定性(NBTI)或是熱載子的注入，或是電子的遷移現象，而對電路的影響來說，這些有可能會造成電路的性能表現降低，或是對於電路的運作造成威脅，造成一些不可預期的錯誤發生。因此，電路老化測試在確保晶片品質的角色上日益重要。
我們提出了一個方法，採用非侵入式的監測方式，連續偵測在目標點的過渡時間。我們的方法是附加一個監視器，連接在電路邏輯閘的輸出端，上升和下降的過渡時間會被轉換成一個脈衝寬度，然後進一步轉化成二進制表示,最後再由監測中心收集和計算出最後數值，此數值和目標點所量測出的過渡時間會呈現正相關的關係。在過渡時間量測的部分，我們使用一個改良的時間至數位轉換器 (time-to-digital converter)。此外，我們透過模擬的附加邏輯元件(CMOS元件)來調整測試模式下的驅動強度，可模擬電路老化的現象，並由監視器偵測出，過渡時間會隨著元件的驅動能力而變化，根據Nanosim的模擬結果，當元件的驅動能力變弱，意味著電路發生老化的現象，而量測出的過渡時間數值也會隨之變大。我們以 TSMC 90nm製程來實現。

The aging of circuit will affect the transistor in Negative-Bias Temperature Instability (NBTI) and hot carrier injection and electron migration, which may cause the performance degradation and unexpected failure of the circuit. Therefore, detecting these defects is often necessary in modern testing.
We propose a method to continuous detect the transition time on the target point. Our approach is to attach a monitor on the output of the logic gate. The rise and fall transition time is converted into a pulse width, and then further converted to the binary code. In the measurement of the access time, we use a time-to-digital converter. In addition, through an additional element to adjust the drive strength, to simulate the aging phenomenon, the monitor can detect the change in the transition time. We implement it in TSMC 90nm CMOS technology.

[1]S.-Y. Huang, M.-T. Tsai, H.-X. Li, Z.-F. Zeng, K.-H. (Hans) Tsai, and W-.T. Cheng, "Non-Intrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects," IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD).
[2]M.-T. Tsai, S.-Y. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Monitor the Delay of Long Interconnects via Distributed TDC," Proc. of IEEE Int'l Test Conf., (Oct. 2015).
[3]T. Frank, S. Moreau, C. Chappaz, L. Arnaud, P. Leduc, A. Thuaire, and L. Anghel, "Electromigration Behavior of 3D-IC TSV Interconnects", Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp.326-330, June 2012.
[4]T. Frank, C. Chappaz, P. Leduc, L. Arnaud, F. Lorut, S. Moreau, A. Thuaire, R. El Farhane, and L. Anghel, “Resistance Increase Due to Electromigration Induced Depletion under TSV", Proc. of IEEE Int'l Reliability Physics Symp. (IRPS), pp. 3F.4.1-3F.4.6, April 2011.
[5]K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. S. Ho, “Thermal Stress Induced Delamination of Through Silicon Vias in 3D Interconnects," Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp. 40-45, June 2010.
[6]C. Serafy and A. Srivastava, "Online TSV Health Monitoring and Built-In Self-Repair to Overcome Aging", Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 224-229, 2013.
[7]L. Jiang, F. Ye, Q. Xu, K. Chakrabarty, and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs," Proc. of Design Automation Conf, pp. 1-6, 2013.
[8]K. Chakrabarty, “TSV Defects and TSV-Induced Circuit Failures: The Third Dimension in Test and Design-for-Test”, Proc. of Int’l Reliability Physics Symp., (IRPS), pp. 5F1.1-5F.1.12, 2012.
[9]Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[10]Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[11]F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation”, Proc. of Design Automation Conf., pp. 10240-1030, June 2012.
[12]S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 8, pp. 1258-1268, Aug. 2014.
[13]S.-Y. Huang, H.-X. Li, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs", Proc. of Asian Test Symp. (ATS), pp. 162-167, Nov. 2014.
[14]J. Carretero, X. Vera, P. Chaparro, and J. Abella, “Microarchitectural Online Testing for Failure Detection in Memory Order Buffer”, IEEE Trans. on Computers, Vol. 59, No. 5, pp. 623-637, 2010.
[15]Y. Li, Y. M. Kim, E. Mintarno, D. S. Gardner, and S. Mitra, “Overcoming Early-Life Failure and Aging for Robust Systems,” IEEE Design & Test of Computers, Vol. 26, No. 6, pp. 28-39, 2009.
[16]T. H. Kim, R. Persaud, and Chris H. Kim. "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 874-880, 2008.
[17]S. L. Wright, et al, "Characterization of Micro-bump C4 Interconnects for Si-Carrier SOP Applications," Proc. of Electronic Components and Technology Conf., pp. 633-640, 2006.
[18]S. L. Wright, et al, "Micro-interconnection Reliability: Thermal, Electrical and Mechanical Stress", Proc. Electronic Components and Technology Conf., pp. 1278-1286, May 2012.
[19]P. Chen, S.-I. Liu, and J. Wu, “A CMOS Pulse Shrinking Delay Element for Time Interval Measurement,” IEEE Trans. on Circuit and System II, vol. 47, no. 9, pp. 954-958, Sept. 2000.
[20]“CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.
[21] S.-Y. Huang, H.-X. Li, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs", Proc. of Asian Test Symp. (ATS), pp. 162-167, (Nov. 2014)
[22] Y. Li, Y. M. Kim, E. Mintarno, D. S. Gardner, and S. Mitra, “Overcoming Early-Life Failure and Aging for Robust Systems,” IEEE Design & Test of Computers, Vol. 26, No. 6, pp. 28-39, 2009.
[23] F. Corno, M. S. Reorda, G. Squillero, “RT-level ITC’99 benchmarks and first ATPG results”, IEEE Design & Test of Computers, Vol. 17, No. 3, pp. 44-53, 2000.