結合暫停開關電路和直接記憶體存取控制器之增強串列周邊介面匯流排通訊

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研究生：	張國輝 Chang, Guo-Huei
論文名稱：	結合暫停開關電路和直接記憶體存取控制器之增強串列周邊介面匯流排通訊 Enhanced SPI Communication by Combining Pause-Switch Circuit and Direct Memory Access Controllers
指導教授：	周百祥 Chou, Pai H.
口試委員:	蔡明哲 Tsai, Ming-Jer 易志偉 Yi, Chih-Wei
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	44
中文關鍵詞：	序列周邊介面、暫停開關電路
外文關鍵詞：	SPI, Pause-Switch Circuit
相關次數：	點閱：3 下載：0
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本論文擴展了在串列周邊介面（SPI）匯流排上被動裝置到被動裝置交易接合技術。交易接合技術可以完全重疊大量傳輸，而且效能幾乎增加了標準的串列周邊介面的一倍。雖然直接記憶體存取（DMA）控制器無法不透過記憶體實現從被動裝置到被動裝置的傳輸，但它可以減少微處理器控制串列周邊介面的費用。
結合交易接合技術和直接記憶體的效能超過標準的串列周邊介面的五倍，它還降低能源消耗且不需要任何記憶體暫存資料。我們以最低的硬體和軟軟開銷描述了一個真正實作並且同時保留完全兼容現有的串列周邊介面設備。在實作上使用了複雜可程式邏輯裝置（CPLD），實作結果得知只需幾個邏輯單元即可，因此我們只需極少的成本即可集成到一個晶片上，如微處理器。我們介紹了實際世界的案例研究，其中包括12導聯心電圖系統，當使用的低端微控制器，該系統是非常需要的增強型串列周邊介面，否則就會有串列周邊介面效能的瓶頸。藉由使用低端微控制器，它可以達到省電和和節省成本的功效，而且使用我們的方法，串列周邊介面的效能是高於高端微控制器使用標準串列周邊介面的效能。實驗結果可以發現改善了450％的延遲和處理能力。藉由消除這個瓶頸，幾乎所有基於串列周邊介面的設計中，我們可以節省電能且同時滿足延遲和處理能力的要求。

This thesis extends a transaction-splicing technique for slave-to-slave transfers on the Serial Peripheral Interface (SPI) bus. Transaction-splicing technique can completely overlap in the bulk transfer, thereby nearly doubling the performance of standard SPI bus transaction. Although direct memory access (DMA) controllers cannot perform slave-to-slave transfers without going through the memory, it can decrease the MCU overhead of SPI bus transactions.
The combination of splicing transactions and involving DMA is more than quintuples the performance of standard SPI bus transaction. It also decreases energy consumption and does not need any memory to cache data. We describe a real implementation with minimal hardware and software overhead while retaining full compatibility with existing SPI devices. It is implemented with a dedicated CPLD, and it can be integrated into a chip such as a microcontroller with few minimal additional cost of only a few logic cells. We present real-world case studies including a 12-lead ECG system, which is sorely in need of enhanced SPI when implemented using low-end MCUs, which would otherwise have plenty of performance without the SPI bottleneck. By using low-end MCUs, it can enable power and cost savings, and the performance of SPI bus transactions with our work is higher than that of high-end MCUs. The evaluation can present about 450% improvement in latency and throughput. By eliminating this bottleneck in virtually all SPI-based designs, we are able to save power while meeting both latency and throughput requirements.

Abstract i
Contents i
Acknowledgments vi
Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . 1
2 SPI Bus Transaction with DMA controllers . .  .  . 2
3 Transaction Splicing . . . . . . . . . . . . . . . 2
4 Contributions . . . . .. . . . . . . . . . . . . . 3
5 Organization . . . . . . . . . . . . . . . . . . . 3
Background 4
1 SPI . . . . . . . .  . . . . . . . . . . . . . . . 4
2 Double-Transaction Problem . . . . . . . . . . . . 5
3 MCU Overhead . . . . . . . . . . . . . . . . . . . 5
Related Work 7
1 DMA, QSPI, and Multiple-SPI . . . . . . . .  . . . 7
2 Enhanced SPI Bus Communication with PSC . . . .. . 8
3 I2C . . . . . .. . . . . . . . . . . . . . . . . . 9
Technical Approach 11
1 SPI Bus Transactions with DMA Controllers . . .  . 11
2 Combining DMA with a PSC in SPI Transactions .  .  12
3 SCK Generation by PSCs . . . . . . . . . . . . . . 13
4 Scalability of Switched SPI Bus . . . . . . . . .  14
Implementation 16
1 Dedicated CPLD . . . . . . . . . . . . . . . . . . 16
2 Combining DMA with PSCs . . . .  . . . . . . . . . 19
3 Fully Embedded PSC . . . . . . . . . . . . . . . . 20
Case Study 22
1 Application: Wearable ECG . . . . . .  . . . . . . 22
2 System Designs . . . . . . . . . . . . . . . . . . 24
Evaluation 29
1 Latency . . . .. . . . . . . . . . . . . . . . . . 29
2 Throughput . . . . . . . . . . . . . . . . . . . . 33
3 Energy Savings . . . . . . . . . . . . . . . . . . 36
4 Improvement by involving DMA . . . . . . . . . . . 38
Conclusions and Future Work 42
1 Conclusions . . .  . . . . . . . . . . . . . . . . 42
2 Future Work . . . . . .  . . . . . . . . . . . . . 43

                                

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