隨著生物電子領域的快速發展，許多生物電子系統 ( Bio-electronic System )都已結合積體電路作成植入式元件 (Implantable Device) [1][2]，並被廣泛應用在生物醫學領域。然而在充滿雜訊的生醫環境底下，元件內的生物電子系統必須要有相當的雜訊抵抗能力，才能夠確保生物晶片植入生物體內後能夠不受雜訊干擾正常運作。而其中「連續值侷限型波茲曼模型」(Continuous Restricted Boltzmann Machine，以下簡稱 CRBM )就是一種被認為相當具有發展潛力的可靠模型，因為這類模型的系統架構採用機率型輸出，比起採用傳統決定性 (Deterministic) 輸出的模型而言，將擁有更佳的計算錯誤容忍度，因此更適合在充滿雜訊的生醫環境底下工作。
隨著CMOS製程的微小化以及SOC的發展應用日漸成熟，將來類比訊號的生物電子系統勢必會與數位電路整合至同一晶片上，而數位電路的訊號較強，很可能透過基版 (Substrate) 的訊號耦合而干擾到同一晶片上的生物電子系統。因此，本論文的研究目標就是研究基板雜訊對CRBM系統的效能影響，並模擬檢驗CRBM系統對於基板雜訊的雜訊容忍值。
本論文研究是採用許多不同的環境設定去模擬基板雜訊對CRBM系統在二維人工資料的建模 (Modeling) 以及多維人工資料的辨識 (Classifying)之影響，從模擬的結果我們可以得知CRBM系統的雜訊容忍力頗佳，即使是對於伴隨偏移所產生的雜訊，也有相當優秀的抵抗能力。此外本研究也發現CRBM系統有可能可以利用電晶體內部雜訊或是其他雜訊來源來執行電路運算之可能性，提供了將來改善CRBM系統架構的另一個研究方向。

[1] T.B.Tang, M.Ahmadian, A.F.Murray, A.Astaras, L.Wang, J.M.Cooper, S.P.Beaumont, B.W.Flynn, and D.R.S.Cumming, “Toward a miniature wireless integrated multisensor microsystem for industrial and biomedical applications,” IEEE Sens.J.Special Issue on Integr.Multisensor Syst.Signal Process., vol. 2, no.6, pp. 628-635, 2002.
[2] E.A.Johannessen, L.Wang, S.W.Reid, D.R.S.cumming, L.Cui, T.B.Tang, M.Ahmadian, A.Astaras, P.Yam, A.F.Murray, B.W.Flynn, S.P.Beaumont, and J.M.Cooper, “Implementation of distributed sensors in a microsystems format,” IEEE Trans.Biomed.Eng., vol. 51, no.3, pp.525-535, 2004.
[3] M.A.L.Nicolelis, “Actions from thoughts,” Nature, vol. 409 pp.403-407,2001.
[4] M.Sun, M.Micklem L.Wei, Q.Liu, and R.Sclabassi, “Data communication between brain implants and computer,” IEEE Trans. Neural Syst, vol. 11, no. 2, pp. 189-192, 2003.
[5] Chen, H. and Murray, A. F., “Continuous restricted Boltzmann machine with an implementable training algorithm,” Iee Proceedings-Vision Image and Signal Processing, vol. 150, no. 3, pp.153-158, 2003.
[6] Chen, H, “Continuous-valued Probabilistic Neural Computation in VLSI,” PhD Thesis, Edinburgh University, UK, 2004.
[7] Chen, H., Fleury, P., and Murray, A. F., “Continuous-Valued Probabilistic Behaviour in a VLSI Generative Model, ” IEEE Transactions on Neural Networks, vol. 17, no. 3, pp. 755-770, 2006.
[8] G. E. Hinton, “Training products of experts by minimizing contrastive divergence,” Neural Computation, vol. 14, no. 8, pp. 1771-1880, 2002.
[9] H. Wang, “Low-frequency noise study in electron devices: review and update,” Microelectronic Reliability, vol. 43, pp. 585-599, 2003.
[10] M. Valenza, A. Hoffmann, D. Sodini, A. Laigle, F. Martinez, and D. Rigaud, “Overview of the impact of downscaling technology on 1/f noise in p-mosfets to 90nm,” IEEE Proc. Circuits, Devices, and Systems, vol. 151, pp. 102-110, April 2004.
[11] Tsun-Lai Hsu, Yu-Chia Chen, Hua-Chou Tseng, V. Liang, J.S. Jan, “psub guard ring design and modeling for the purpose of substrate noise isolation in the SOC era,” IEEE Electron Device Letter, vol 12, pp. 693-695, September 2005.
[12] M. Nagata, J.Nagai, K.Hijikata, T.Morie, A.Iwata, “Physical design guides for substrate noise reduction in CMOS digital circuits,” IEEE Journal of Solid-State Circuits, vol 36, pp. 539-549, March 2001.
[13] M.Van Heijningen, J.Compiet, P.Wambacq, S.Donnay, M.G.E.Engels, I.Bolsens, “Analysis and experimental verification of digital substrate noise generation for epi-type substrates,” IEEE Journal of Solid-State Circuits, vol 35, pp. 1002-1008, July 2000.
[14] Mark Shane Peng and Hau-Seung Lee, “Study of substrate noise and techniques for minimization,” IEEE Journal of Solid-state Circuits, vol. 39, no. 11, November 2004.
[15] G. Blakiewicz, M.Jeske, M.Chrzanowska-Jeske, “Substrate noise optimization in early floorplanning for mixed signal SOCs,” IEEE International SoC Conference, pp. 301-304, September 2004.
[16] Kazama Taisuke, Nakura Toru, Ikeda Makoto, Asada Kunihiro, “Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector,” IEEE Asian Solid-State Circuit Conference, pp. 239-242, November 2006.
[17] M. Felder, J. Ganger, “Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip,” IEEE Circuit and System Transaction, vol 46, pp. 1427-1436, November 1999.
[18] Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, A. Iwata , “Chip-level substrate noise analysis with network reduction by fundamental matrix computation,” IEEE Quality Electronic Design International Symposium, pp. 492-487, March 2001.
[19] G. Blakiewicz, M. Chrzanowska-Jeske, “Modeling of substrate noise block properties for early prediction,” IEEE Circuit and System International Symposium, vol 3, pp. 3015-4018, May 2005.

[20] Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, and Hugo J. De Man, “Evolution of substrate noise generation mechanisms with CMOS technology scaling,” IEEE Transactions on Circuits and Systems-I: regular papers, vol. 53, no. 2, February 2006.
[21] M. Van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, I. Bolsens, “Modeling of digital substrate noise generation and experimental verification using a novel substrate noise sensor,” IEEE European Solid-State Circuit Conference, pp. 186-189, November 1999.
[22] M. Van Heijningen, M. Badaroglu, S. Donnay, G.G.E. Gielen, H.J. De Man, “Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification,” IEEE Journal of Solid-State Circuits, vol 37, pp. 1065-1072, August 2002.
[23] T. Pompl, M. Kerber, G. Innertsberger, KH. h e r s , M. Obry, A.Kriemann, D. Temmle, “Modeling of substrate related extrinsic oxide failure distributions,” IEEE International Reliability Physics Symposium, Dallas, Texas, 2002.