建構掃描式曝光機台之覆蓋誤差模式與設計取樣策略之實證研究

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研究生：	許嘉裕 Chia-Yu Hsu
論文名稱：	建構掃描式曝光機台之覆蓋誤差模式與設計取樣策略之實證研究 Step-and-Scan Overlay Errors Modeling, Design of Sampling Strategies and the Validation via the Empirical Study
指導教授：	簡禎富 Chen-Fu Chien
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	61
中文關鍵詞：	覆蓋誤差、模式、取樣策略、步進且掃描式機台、半導體製造管理
外文關鍵詞：	overlay error, modeling, sampling strategies, step-and-scan, semiconductor manufacturing
相關次數：	點閱：2 下載：0
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中文摘要

覆蓋誤差精度是影響積體電路製造微影技術的關鍵準則之一，為了提高對準精度與解析度，現有曝光機台技術已由步進式曝光機改良為掃描式曝光機。隨著線寬的容差範圍緊縮，覆蓋誤差必須長期控制在穩定且合乎容忍的範圍內，補償覆蓋誤差一般是經由調整曝光機台之設定參數。然而，覆蓋誤差的精度受到所使用的覆蓋誤差模式影響。雖已有許多的理論模式被提出，但主要都是探討步進式曝光機之模式，只有少數的相關研究探討掃描式曝光機之模式。
本研究目的係回顧並改良掃描式曝光機既有之覆蓋誤差數學模式，並提出相對應模式之取樣策略，並針對曝光機台群組之問題，提出分群之法則。在誤差模式中，我們僅考慮可被校正，且實際尚可被半導體廠的機台量測與補償的誤差因子。驗證所提出之抽樣方法，由實際半導體廠所量得資料，比較不同抽樣策略下之補償效果。評估所提出覆蓋誤差模式之適切度，證明相對應模式取樣策略之效度。

關鍵字：覆蓋誤差、模式、取樣策略、步進且掃描式機台、半導體製造管理

Abstract

In order to meet the requirements of high resolution and alignment accuracy, the lithography equipments have been advanced from step-and-repeat system to step-and-scan system. As the tolerance of linewidths is becoming tight and slight, overlay errors must be controlled within the tolerance to maintain the yield. In particular, overlay errors can be compensated by modifying the corresponding equipment setup parameters. However, most of the existing studies focused on the step-and repeat system. Little research has been done to deal with overlay errors of the step-and-scan system.
This study aimed to construct the overlay error model for step-and-scan system and design the sampling strategy to measure and thus compensate the overlay errors. Furthermore, the proposed model and sampling strategy are validated by empirical studies conducted in a fab. We compared the proposed sampling strategy with alternative sampling strategies including the existing sampling strategies based on the model adequacy of R-squares and the model effectiveness of residual errors. The results demonstrated the practical viability of the proposed approach.

Keywords: overlay, modeling, sampling strategy step-and-scan, semiconductor manufacturing

Table of Content

Table of Content    i
List of Figures    ii
List of Tables    iii
Chapter 1 Introduction    1
1.1 Background, Significance, and Motivation    1
1.2 Research aims    2
1.3 Overview of this thesis    3
Chapter 2 Literature Review    4
2.1 Advanced process control    4
2.2 Lithography Technology and Tool    5
2.2.1 Step-and-Scan System Versus Step-and-Repeat System    6
2.3 Overlay and Theoretical overlay model    9
2.3.1 Overlay errors    9
2.3.2 Existing Stepper overlay error models    14
2.3.3 Existing Scanner overlay error models    19
2.4 Sampling Strategies    23
Chapter 3 Research Framework    25
3.1 Problem Definition and Problem structuring    25
3.2 A Conceptual framework    25
3.3 Develop a scanner overlay model    30
3.3.1 Cause and effect simulation    30
3.3.2 Develop scanner overlay error model    35
3.4 Proposed sampling strategies    40
3.4.1 Cause and effect for sampling patterns    40
3.4.2 The design of sampling patterns    44
Chapter 4 An Empirical Study    47
4.1 Experimental design    47
4.2 Revised the existing sampling pattern    48
4.3 Intrafield sampling strategies    49
4.4 Interfield sampling strategies    50
4.5 Evaluation of the proposed model and integrated sampling strategies    52
Chapter 5 Conclusion    56
References    58

List of Figures

Figure 1.1 the overall research process    3
Figure 2.1 the step-and-repeat and scan-and-step lateral view    8
Figure 2.2 causes-and-effects of overlay errors    9
Figure 2.3 the overlay error measurement (Chien et al 2003)    11
Figure 2.4 the intrafield overlay errors    12
Figure 2.5 the interfield overlay errors    13
Figure 3.1 a conceptual framework    27
Figure 3.2 design of sampling strategies flowchart    29
Figure 3.3 the individual factors of intrafield overlay errors    31
Figure 3.4 the combined factors of intrafield overlay errors    32
Figure 3.5 the individual factors of interfield overlay errors    33
Figure 3.6 the combined factors of interfield overlay errors    34
Figure 3.7 the intrafield overlay sampling locations    40
Figure 3.8 the interfield overlay sampling fields    42
Figure 3.9 intrafield sampling patterns    44
Figure 3.10 interfiled sampling patterns    46
Figure 4.1 the overlay location of empirical data    47
Figure 4.2 (a) Residual analysis of 20 sampled overlays (b) Residual analysis of 2295 sampled overlays    53
Figure 4.3 Histogram of residuals of the proposed and existing sampling strategies (20 overlays)    55

List of Tables

Table 2.1 product critical level lithography requirements (SIA 1997)    7
Table 2.2 the advantages of step-and-scan system    8
Table 2.3 considered overlay error factors    22
Table 3.1 the relation of regression coefficients and overlay model parameters    39
Table 4.1 R-squares and error norms of different sampling numbers    49
Table 4.2 R-square and error norms of different intrafield sampling patterns    50
Table 4.3 R-squares and error norms of different interfield sampling patterns    51
Table 4.4 Error norms of proposed and existing sampling patterns with different sampling numbers    54

                                

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