研究生: |
李宗賢 Tsung-Hsien Lee |
---|---|
論文名稱: |
全域繞線下考慮接點最小化之層分配 Congestion-constrained layer assignment for via minimization in global routing |
指導教授: |
王廷基
Ting-Chi Wang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 中文 |
論文頁數: | 70 |
中文關鍵詞: | 全域繞線 、層分配 |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在這篇論文裡面,我們考慮全域繞線下的最小層分配。我們將一個初步給定的一層結果中的溢滿總量和最大溢滿當做給定的壅塞條件,並且希望在這種環境下找到接點最小化的層分配。為了解決這個問題,我們提出一個演算法先產生一個電路順序然後依序使用動態規劃將每個電路問題解決
我們採用ISPD 2007全域繞線比賽的測試資料來測試我們的演算法,而實驗結果顯示我們的方法對於目前最先進的繞線器MaizeRouter平均可以達到7.77%,BoxRouter達到16.69%,以及FGR達到2.11%的接點最小化之層分配改善。
Abstract
In this thesis, we study the problem of layer assignment for via minimization that arises during multi-layer global routing. In this problem, we take total overflow and maximum flow as the congestion constraints from an initial one-layer routing solution and we want to find a layer assignment result for each net such that the via cost is as small as possible while the given congestion constraints are satisfied. This layer assignment problem is different from the well-known constrained via minimization problem that is handled after detailed routing. To solve this problem, we propose a sequential algorithm which first generates a net order, and then according to the order, performs layer assignment one net at a time by using dynamic programming
We use the benchmarks released from the ISPD’07 global routing contest to test our algorithm, and the experimental results show that our algorithm can get averagely 7.77%, 16.69%, and 2.11% improvement rates on the via cost as compared to three state-of-the-art multi-layer global routers, MaizeRouter, BoxRouter and FGR, which were known to the top three winners of the multi-layer category at the ISPD’07 global routing contest.
[1] R. Kastner, E.Bozogzadeh, and M. Sarrafzadeh, “Predictable Routing,” Proceedings of International Conference on Computer-Aided Design, pp. 110-113, 2000.
[2] M. Pan and C. Chu, “FastRoute: A Step to Integrate Global Routing into Placement,” Proceedings of International Conference on Computer-Aided Design, pp. 464-471, 2006.
[3] M. Pan and C. Chu, “FastRoute 2.0: A High-quality and Efficient Global Router,” Proceedings of Asia and South Pacific Design Automation Conference, pp.250-255, 2007.
[4] M. Cho and D. Z. Pan, “BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP,” Proceedings of Design Automation Conference, pp. 373-378, 2006.
[5] C. Sechen and A. Sangiovanni-Vincentelli, “The TimberWolf Placement and Routing Package,” IEEE Journal of Solid-State Circuits, Vol. 20, No. 2, pp. 510-522, 1985.
[6] H. Shin and A. Sangiovanni-Vincentelli, “Mighty: A ‘Rip-Up and Reroute’ Detailed Router,” Proceedings of International Conference on Computer-Aided Design, pp. 115-122, 1986.
[7] L.E. Liu and C. Sechen, “Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 10, pp. 1442-1451, 1997.
[8] M.J. Ciesielski, “Layer Assignment for VLSI Interconnect Delay Minimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, No. 6, pp. 702-707, 1989.
[9] J.D. Cho, S. Raje, M. Sarrafzadeh, M. Sriram, and S.M. Kang, “Crosstalk-Minimum Layer Assignment,” Proceedings of Custom Integrated Circuits Conference, pp. 29.7.1-29.7.4, 1993.
[10] D. Wu, J. Hu, R. Mahapatra, and M. Zhao, “Layer Assignment for Crosstalk Risk Minimization,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 159-162, 2004.
[11] K. Ahn and S. Sahni, “Constrained Via Minimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 2, pp. 273-282, 1993.
[12] C.C. Chang and J. Cong, “An Efficient Approach to Multilayer Layer Assignment with Application to Via Minimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 5, pp. 608-620, 1999.
[13] N.J. Naclerio, S. Masuda, and K. Nakajima, “The Via Minimization Problem is NP-Complete,” IEEE Transactions on Computers, Vol. 38, No. 11, pp. 1604-1608, 1989.
[14] K.C. Chang, and H.C. Du, ”Layer Assignment Problem for Three-Layer Routing,” IEEE Transactions on Computers, Vol. 37, No. 5, pp.625-632, 1988.
[15] T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, Introduction to Algorithms, 2nd edition, McGraw-Hill, 2001.
[16] G.J. Nam, ISPD 2007 Global Routing Contest, 2007.
http://www.ispd.cc/rcontest/
[17] M.D. Moffitt, University of Michigan, 2007.
[18] J.A. Roy and I.L. Markov, University of Michigan, 2007.
[19] R. Kastner, E. Bozorgazadeh, and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 7, pp.777-790, 2002.
[20] J. Westra, P. Groeneveld, T. Yan, and P.H. Madden, “Global Routing: Metrics, Benchmarks, and Tools,” IEEE DATC of Electronic Design Process, 2005.