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研究生： 林科宏
Lin, Ko-Hong
論文名稱： 基於兩相位鎖延遲迴路且可容忍製程電壓溫度變異的倍頻電路並使用循環脈衝縮減時間量化器進行抖動學習
PVT-Resilient Frequency Doubling Circuit based on Two-Phase DLL using Cyclic TDC-based Jitter Learning
指導教授： 黃錫瑜
Huang, Shi‐Yu
口試委員: 呂學坤
Lu, Shyue-Kung
盛鐸
Sheng, Duo
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2024
畢業學年度： 112
語文別： 英文
論文頁數： 34
中文關鍵詞： 抖動學習 、倍頻器 、可容忍製程電壓溫度變異
外文關鍵詞： Jitter Learning, Frequency Doubling Circuit, PVT-Resilient
相關次數： 點閱：4  下載：0 
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    • 這篇論文介紹了一種基於鎖延遲迴路的數位倍頻電路。它透過由鎖延遲迴路所產生的兩相時脈信號經由或閘合併，從而產生一個倍頻時脈信號，並利用基於循環時間量化器的抖動學習來減輕兩個延遲路徑之間的不匹配。運行中的時脈訊號,經由循環時間量化器量化後,便可以透過控制器判斷當前時脈的品質,並做出適當的調整。此倍頻器輸出時脈的頻率範圍為 1.48GHz 至 2.1GHz。2GHz 輸出時脈的模擬均方根抖動值和峰值到峰值抖動值分別僅為 1.51皮秒 和 8皮秒。所提出數位倍頻電路在90 奈米製程下的面積為 0.054〖 mm〗^2，2GHz 時的功耗為 12.4 毫瓦。

    This thesis presents a digital DLL-based Frequency Doubling Circuit. It merges two phases of the clock signal produced by DLL via an OR gate to create a doubled clock and uses cyclic TDC-based Jitter Learning to mitigate the mismatch between two delay paths. During the operation, the clock signal, once quantified by a cyclical TDC, enables the controller to assess the current clock quality and make the necessary adjustments. The frequency ranges of the output clock are 1.48 GHz~2.1 GHz. The simulated RMS and peak-to-peak jitter values of the 2Ghz output clock are only 1.51ps and 8ps, separately. The proposed 90nm all-digital Frequency doubling circuit occupies an active area of 0.054 mm2 and consumes 12.4mW at 2Ghz.

    Abstract ii 摘要 iii Content iv List of Figures v List of Tables vii Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Thesis Organization 5 Chapter 2 Preliminaries 5 2.1 Relative work 6 2.2 Introduction and operation of Baseline FDC 9 Chapter 3 Proposed FDC using jitter learning 13 3.1 New Architecture of FDC using Cyclic TDC-based Jitter Learning 13 3.2 Delay Tuning with Varactor Cell Group 15 3.3 Overall Operation Flow 16 Chapter 4 Experiment Results 20 4.1Experiment Result of Baseline FDC 20 4.2 Experiment Result of FDC using Cyclic TDC-based Jitter Learning 25 Chapter 5 Conclusion 30 References 32

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