隨著半導體技術進步，金氧半積體電路操作電壓由以往的5V，3.3V降至2.5V，在90 nm製程技術之後，操作電壓已經降至1.2V。在現今的積體電路技術中，這些精密的電晶體變的對於靜電放電以及暫態電壓越來越敏感。因此，用於靜電放電以及暫態電壓防護用的保護元件的額定工作電壓也應隨之降低，以提供適當的保護。
用於防護靜電放電以及暫態電壓的保護元件，依照其保護的對象，可粗分為兩類：電源供應線以及資料傳輸線。對於電源供應線的保護元件，主要的需求在於適當的崩潰電壓以及低漏電流。然而，在降低崩潰電壓時常伴隨著漏電電流的上升。另一方面，資料傳輸線上之保護元件的則需要低電容，以避免影響到資料傳輸線上的資料傳輸速度以及資料正確性。
在本論文中分為兩部分：第一部分是對現有的暫態電壓保護元件的改良，抑制在降低崩潰電壓時伴隨而生的漏電流。就現有元件的漏電抑制部分，利用全面性的反態離子佈殖降低元件週邊摻雜濃度，此種方法可以降低元件週邊的電場達到降低因能帶穿隧效應引起的漏電流。此種方法可以利用極少的製程變化達到改善產品性能的效果。在低電容方面，由於具有單一接面的二極體元件其崩潰電壓以及接面電容的關係受到物理上的限制。新的元件採用具有電場增強效果的結構降低崩潰電壓，突破崩潰電壓以及接面電容的物理限制。另一種方法則是利用串連兩個二極體所組成的元件，以降低電容值。此外，由於傳統上用於保護元件的二極體，其順偏操作下可承受的電流高於逆偏操作，並利用非對稱性的結構更進一步的改善低電容靜電防護以及暫態電壓保護元件的低電容特性。

As complementary metal-oxide semiconductor (CMOS) technology progresses, the supply voltage drops from 5V and 3.3V to 2.5 V or even lower than.1.2 V for CMOS technology beyond the 90 nm technology node. The delicate transistors in modern integrated circuits (ICs) are becoming more sensitive to transient voltage stress or electrostatic discharge. Hence, the rating voltage of the corresponding protection device should be reduced to accommodate these changes.
For power line protection, the leakage caused by band-to-band tunneling in low-voltage transient voltage suppressor (TVS) devices would be a major problem. For data line protection, one key feature is to maintain low capacitance of these TVS devices to prevent interference with the protected circuits.
In this dissertation, there are two targets: the improvement on leakage for commercially available low-voltage TVS devices and the design of new TVS structure to effectively reduce the overall capacitance. A simple method of blanket-ion implantation is used to reduce leakage in low-voltage TVS. By adapting electric field enhancement structure, the breakdown voltage can be reduced and the relationship between the breakdown voltage and junction capacitance on conventional TVS diodes can be broken. A device with two junctions in series is another way to reduce the capacitance. Based on the current capability difference between forward and reverse biased diodes, an asymmetry structure is also used to further reduce the overall capacitance and increase the current handling capability of the two-junction device.

Chapter 1
[1.1] ITRS Roadmap
[1.2] Ya-chin King, Bin Yu, Jeff Pohlman, and Chenming Hu, “Punchthrough Diode as the Transient Voltage Suppressor for Low-Voltage Electronics”, IEEE Trans. on Electron Devices, Vol. 43, No. 11, pp. 2037-2040, 1996
[1.3] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor,” Proc. International Semiconductor Conference (CAS'99), pp. 169-172
[1.4] B. Jayant Baliga, Power Semiconductor Devices, Boston, MA: PWS, 1996. pp.82
[1.5] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp.34, 94, 244-245
[1.6] E. O. Kane, “Zener Tunneling in Semiconductors,” J. Phys. Chem. Solids, Vol. 12, pp. 181-188, 1959
[1.7] Richard B. Fair and Hayden W. Wivell, “Zener and Avalanche Breakdown in As-Implanted Low Voltage Si n-p Junctions,” IEEE Trans. Electron Devices, Vol. ED-23, No. 5, pp. 512-518, May 1976
[1.8] Universal Serial Bus (USB) Revision 2.0 specification
[1.9] High-Definition Multimedia Interface (HDMI) Specification Release 1.3
[1.10] Intel□ Packaging Databook, Chapter 6 ESD/EOS: An overview of electrical static discharge and electrical over stress, 2000

[1.11] Corey Lewis, Bilal Abd-AlRahman, and Todd Simons, “Electrical Overstress (EOS) in Semiconductor Devices: How to differentiate and document EOS due to over-current or over-voltage”, 31st International Symposium for Testing and Failure Analysis (ISTFA), Nov 6-10, 2005, San Jose, USA
[1.12] Ming-Dou Ker and Chung-Yu Wu, “Complementary-SCR ESD Protection Circuit with Integrated Finger-Type Layout for Input Pads of Submicron CMOS IC’s”, IEEE Trans. Electron Device, Vol. 43, No. 7, pp. 1297-1304, 1995

Chapter 2
[2.1] STMicroelectronics, TVS Catalog, SMLVT3V3
[2.2] Vishay, TVS Catalog, SMBJ3V3, MSP3V3
[2.3] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor”, Proc. International Semiconductor Conference (CAS'99), pp. 169-172
[2.4] Ya-chin King, Bin Yu, Jeff Pohlman, and Chenming Hu, “Punchthrough Diode as the Transient Voltage Suppressor for Low-Voltage Electronics”, IEEE Trans. on Electron Devices, Vol. 43, No. 11, pp. 2037-2040, 1996
[2.5] B. Jayant Baliga, Power Semiconductor Devices. Boston, MA: PWS, 1996. pp.82
[2.6] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, pp.34, 94, 244-245, 1998,
[2.7] E. O. Kane, “Zener Tunneling in Semiconductors”, J. Phys. Chem. Solids, Vol. 12, pp. 181-188, 1959

[2.8] Richard B. Fair and Hayden W. Wivell, “Zener and Avalanche Breakdown in As-Implanted Low Voltage Si N-P Junctions”, IEEE Trans. Electron Devices, Vol. ED-23, No. 5, pp. 512-518, May 1976
[2.9] Intel□ Packaging Databook, Chapter 6 ESD/EOS: An overview of electrical static discharge and electrical over stress, 2000
[2.10] Corey Lewis, Bilal Abd-AlRahman, and Todd Simons, “Electrical Overstress (EOS) in Semiconductor Devices: How to differentiate and document EOS due to over-current or over-voltage”, 31st International Symposium for Testing and Failure Analysis (ISTFA), Nov 6-10, 2005, San
[2.11] D. C. Wunsch and R. B. Bell, “Determination of Threshold failure Levels of Semiconductor Diodes and Transistors due to Pulse Voltage”, IEEE Trans. Nuclear Science, Vol. 15, Issue 6, pp. 244-259, December 1968
[2.12] Steven H. Voldman: ESD Physics and Devices (John Wiley & Sons, UK, 2004), p. 60

Chapter 3
[3.1] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor,” Proc. International Semiconductor Conference (CAS'99), pp. 169-172
[3.2] B. Jayant Baliga, Power Semiconductor Devices. Boston, MA: PWS, 1996. pp.82
[3.3] P. Smeys, P. B. Griffin, Z. U. Rek, I. De. Wolf, and K. C. Saraswat, “The influence of process-induced stress on device characteristics and its impact on scaled device performance”, in IEDM Tech. Dig., 1996, pp.709–712.

[3.4] P. Smeys, P. B. Griffin, Z. U. Rek, I. De. Wolf, and K. C. Saraswat, “Influence of process-induced stress on device characteristics and its impact on scaled device performance”, IEEE Trans. on Electron Devices, Vol. 46, no. 6, pp. 1245-1252, June 1999
[3.5] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp.94
[3.6] E. O. Kane, “Zener Tunneling in Semiconductors,” J. Phys. Chem. Solids, Vol. 12, pp. 181-188, 1959
[3.7] Richard B. Fair and Hayden W. Wivell, “Zener and Avalanche Breakdown in As-Implanted Low Voltage Si N-P Junctions,” IEEE Trans. Electron Devices, Vol. ED-23, No. 5, pp. 512-518, May 1976
[3.8] STMicroelectronics, TVS Catalog, SMLVT3V3
[3.9] Vishay, TVS Catalog, SMBJ3V3
[3.10] D. C. Wunsch and R. B. Bell, “Determination of Threshold failure Levels of Semiconductor Diodes and Transistors due to Pulse Voltage”, IEEE Trans. Nuclear Science, Vol. 15, Issue 6, pp. 244-259, December 1968

Chapter 4
[4.1] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor,” Proc. International Semiconductor Conference (CAS'99), pp. 169-172
[4.2] Fairchild Semiconductor, TVS Product Catalog
[4.3] On Semiconductor, TVS Product Catalog

[4.4] J. D. Jackson, Classical Electrodynamics, 3rd ed. New York, NY: Wiley, 1999, p.75
[4.5] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp.90-94
[4.6] D. B. Lee, “Anisotropic etching of silicon,” J. Appl. Phys., Vol. 40, No. 11, pp. 4569-4574, 1969
[4.7] Ping-Hei Chen, Hsin-Yah Peng, Chia-Ming Hsieh, and Minking K. Chyu, “The characteristic behavior of TMAH water solution for anisotropic etching on both Silicon substrate and SiO2 layer”, Sensors and Actuators A, Vol. 93, No. 2, pp.132-137, 2001
[4.8] STMicroelectronics, TVS Catalog, SMLVT3V3
[4.9] Vishay, TVS Catalog, SMBJ3V3
[4.10] C. F. Hawkins, J. M. Soden, E. I. Cole Jr., and E. S. Snyder, “The Use of Light Emission in Failure Analysis of CMOS ICs”, Proc. Int. Symp. for Testing and Failure Analysis (ISTFA) (1990), pp. 55-67
[4.11] C. Russ, K. Bock, M. Rasras, I. De Wolf, G. Groeseneken, and H. E. Maes, “Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing”, Microelectronics Reliability, Vol. 39, pp. 1551-1561, 1999

Chapter 5
[5.1] J. D. Cressler, “SiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applications”, IEEE Trans. Microwave and Techniques, Vol. 46, No. 5, pp. 572-589, 1998

[5.2] S. H. Voldman, “ESD Physics and Devices”, Wiley, Chichester, U. K., 2004, pp. 344, 352
[5.3] Ming-Dou Ker and Chung-Yu Wu, “Complementary-SCR ESD Protection Circuit with Integrated Finger-Type Layout for Input Pads of Submicron CMOS IC’s”, IEEE Trans. Electron Device, Vol. 43, No. 7, pp. 1297-1304, 1995
[5.4] Ming-Dou Ker, and Kuo-Chun Hsu, “Overview of On-Chip Electrostatic Discharge Protection Design With SCR-Based Devices in CMOS Integrated Circuits”, IEEE Trans. Device and Materials Reliability, Vol. 5, No. 2, pp. 235-249, 2005
[5.5] B. J. Baliga, “Power Semiconductor Devices”, PWS Publishing, Boston, MA, 1995, p. 82
[5.6] Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge, U.K.: Cambridge Univ. Press, 1998, pp. 34, 94, 295, 313, 364
[5.7] T. J. Maloney and N. Khurana, "Transmission Line Plising Techniques for Circuit Modeling of ESD Phenomena", EOS/ESD Symposium Proceedings, EOS-7, pp. 49-54, 1985
[5.8] ESD Association Standard Test Method ESD STM5.1 2007, p. 10
[5.9] K. Nikawa, "Optical beam induced resistance change (OBIRCH): overview and recent results", Proc. 16th Annu. Meet. Lasers and Electro-Optics Society (LEOS) 2003. pp. 742-743
[5.10] L. Soon, D. T. M. Ling, M. Kuan, K. W. Yee, D. Cheong, and G. Zhang, “Application of IR-OBIRCH to the Failure Analysis of CMOS Integrated Circuits”, Proc. 10th Int. Symp. Physics and Failure Analysis of Integrated Circuits (IPFA), 2003, pp. 86-91

[5.11] Julian Z. Chen, Ajith Amerasekera, and Tom Vrotsos, “Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/BiCMOS Circuits”, in IEDM Tech. Dig., 1995, pp.337-340

Chapter 6
[6.1] Vasile V.N. Obreja, “Capabilities and Limitations of Semiconductor Surge Voltage Suppressor”, Proc. International Semiconductor Conference (CAS'99), pp. 169-172
[6.2] Ya-chin King, Bin Yu, Jeff Pohlman, and Chenming Hu,” Punchthrough Diode as the Transient Voltage Suppressor for Low-Voltage Electronics,” IEEE Trans. on Electron Devices, Vol. 43, No. 11, pp. 2037-2040, 1996
[6.3] D. A. Neamen: Semiconductor Physics and Devices (McGraw-Hill, New York, 1992), p. 225, p. 274, p. 387
[6.4] D. C. Wunsch and R. B. Bell, “Determination of Threshold failure Levels of Semiconductor Diodes and Transistors due to Pulse Voltage”, IEEE Trans. Nuclear Science, Vol. 15, Issue 6, pp. 244-259, December 1968
[6.5] Sheng-Huei Dai, Jeng-Jie Peng, Chia-Cheng Chen, Chrong-Jung Lin, and Ya-chin King, “Low-Capacitance Low-Voltage Transient Voltage Suppressor by Diode activated SiGe HBT in SiGe HBT BiCMOS Process”, Jpn. J. Appl. Phys., Vol. 48, 04C082, 2009
[6.6] P. Garrou, “Wafer Level Chip Scale Packaging (WL-CSP): An Overview”, IEEE Trans. Adv. Package, Vol. 23, No. 2, pp. 198-205, May 2000
[6.7] H.-M. Hsu, J.-Y. Chang, J.-G. Su, C.-C. Tsai, S.-C. Wong, C. W. Chen, K. R. Peng, S. P. Ma, C. H. Chen, T. H. Yeh, C. H. Lin, Y. C. Sun, and C. Y. Chang, “A 0.18 □m Foundry RF CMOS Technology with 70 GHz FT for Single Cip System Solutions”, IEEE MTT-S Dig. 2001, p.1869-1872
[6.8] J.-G. Su, H.-M. Hsu, S.-C. Wong, C.-Y. Chang, T.-Y. Huang, and Jack Y.-C. Sun, “Improving the RF Performance of 0.18 □m CMOS with Deep n-Well Implantation”, IEEE Electron Device Lett., Vol. 22, pp. 481-483, October 2001
[6.9] Y. Taur, T. H. Ning: Fundamentals of Modern VLSI Devices (Cambridge Univ. Press, Cambridge, U.K, 1998), p. 309-311, 342-347
[6.10] T. J. Maloney and N. Khurana, "Transmission Line Plising Techniques for Circuit Modeling of ESD Phenomena, " EOS/ESD Symposium Proceedings, EOS-7, pp. 49-54, 1985
[6.11] ESD Association Standard Test Method ESD STM5.1 2007, p. 10
[6.12] ON semiconductor, TVS Catalog, ESD11A5.0DT5G
[6.13] Semtech, TVS Catalog, SLVU2.8
[6.14] IEC 61000-4-2, Edition 1.1, 1999, pp. 18, 55
[6.15] C. F. Hawkins, J. M. Soden, E. I. Cole Jr., and E. S. Snyder, “The Use of Light Emission in Failure Analysis of CMOS ICs”, Proc. Int. Symp. for Testing and Failure Analysis (ISTFA) (1990), pp. 55-67
[6.16] C. Russ, K. Bock, M. Rasras, I. De Wolf, G. Groeseneken, and H. E. Maes, “Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing”, Microelectronics Reliability, Vol. 39, pp. 1551-1561, 1999