中文摘要

在晶圓製造過程中會設置許多檢測、量測站用以監控製程參數是否符合規格，希望能及早發現製程問題，將損失減到最小。然而，現今需求量不斷增加，添購檢測機台的成本又很高，如何在檢測機台的有限產能下，提出一套有效之抽樣計畫將有限產能做合理之分配，一直是良率管理(yield management)所關心的議題。對於半導體產業產品生命週期短、產品需求變動大、產業競爭激烈與製造成本高的特性下，降低無附加價值的作業如減少不必要檢驗成本、縮短生產時間，才能提高公司的獲利。
針對晶圓上的缺陷（particle or defect）檢驗已有適當之抽樣檢驗計畫(Nurani et al 1996 and Chien et al 2000)，但對於線寬（critical dimension）、薄膜沈積（thin film）厚度等及時反映在製品度量衡（metrology）品質特性方面，卻少有研究提出完整的抽樣檢驗計畫，在實務上，針對檢驗的樣本大小與抽樣檢驗頻率大多僅依據工程師的經驗作判斷。
本研究針對半導體廠製程中檢驗訂出一套明確且整體的抽樣檢驗計畫，並考慮預防成本、檢驗成本、內部失敗成本、外部失敗成本等品質成本，結合統計抽樣、經濟設計管制圖、品管等理論，針對半導體製程特性並分析歷史資料，以建立以成本為基礎之系統化抽樣策略與統計決策架構，並以敏感度分析方式探討抽樣策略變化對品質成本之影響，並以某半導體廠黃光製程資料進行實證分析，所建立之模式與結果，有效地提供工程師針對不同產品與品質成本，決定最合適的抽樣頻率，以兼顧產能之有效利用與產品良率之提升。
關鍵字：抽樣頻率、抽樣策略、度量衡、檢驗、品值管制

Abstract
A number of inspection and measurement stations are set in the fabrication process to ensure that the quality of wafer meets the requirement. Because of the limited capacities and costs for in-line wafer inspections, only certain wafers are inspected among a specific number of lots.
However, conventional semiconductor wafer fabs meet a variety of economic challenge. The combination of shrinking devices geometries and increasing interconnect levels rapidly increase process complexity, which leads to higher manufacturing costs and longer cycle times.
Although there are many existing studies for IC sampling strategy in defect inspection, little research has been done the issue of metrology sampling. In-line metrology was real time to inspect the WIP. Currently, the sampling metrology numbers and sampling frequency are decided via the engineers’ experience. Thus, different engineers may build various sampling strategies.
This study aims to determine the optimal sampling strategy by developing a risk-based heuristic for statistically determining the sampling strategy for in-line inspection in wafer fabrication. For general defect inspection in wafer fabrication, Nurani et al. (1996) defined five parameters of sampling strategy including layers to be monitored, frequency for lots, and number of inspection wafers per lot, percentage area of the wafer and pixel size. However, for metrology inspection, we combine forth and fifth parameter to another parameter called number of dies in a wafer. Except layers to be monitor, our sampling strategy considers acceptance sampling plan in a wafer and a lot and sampling frequency that tradeoff the various risk (i.e., the aggregation of cost and probability) under different lot size.
Keywords: Bayesian decision analysis, sampling strategy, metrology, inspection, quality control

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