晶片上網路 (NoC) 多核心平台已經在之前被提出來，這個平台上有專門的硬體去支援平行程式所需要的資料傳輸函式庫，但是之前的平台只有支援阻礙式通訊。在阻礙式通訊的過程中，處理核心必須要透過不斷的檢查通訊的狀態以確定通訊完成。在資料傳輸過程中的時間，包含了網路上的傳輸時間、以及流量控制 (flow control) 過程的時間，這些時間會導致較沒有效率的計算資源分配。在這篇論文中，我們提出了一個支援非阻礙式與阻礙式的傳輸。根據硬體的架構也發展出非阻礙式資料傳輸的程式介面 (API) ，讓程式設計者可以使用計算與通訊之間重疊的時間來增加程式的效率。

我們設計的通訊元件以及程式介面環境是在SystemC與TLM下，在這個環境下進行對硬體以及軟體層的開發和驗證。在實驗的結果中我們比較了阻礙式與非阻礙式的傳輸所需要的時間，在單一資料的傳輸中為比例為1.77 (非阻礙式/阻礙式)，在多筆資料的傳輸中為2。此外我們也使用高階合成 (HLS) 的工具幫我們產生出Verilog RTL，在RTL這個層級我們可以得到通訊元件更為精確的時間與面積。

Previously, a Network-on-Chip (NoC) based many-core platform has been proposed. This platform
features a dedicated hardware module to support a message passing communication library
for parallel programming. However, only blocking communication is supported in the previous
platform. During blocking communication, the processor cores have to stop computation and wait
in a busy loop to check communication status. It is possible that a long communication latency
(including waiting time for network transfer and response at the other end) will lead to less efficient
computation resource allocation. In this thesis, we proposed a communication unit which
supports both blocking and non-blocking data transfer. Based on the hardware infrastructure, a set
of non-blocking message passing application programming interface (API) is also developed for
programmers to overlap computation and communication which may improve the overall program
efficiency.
We designed our communication unit and APIs with SystemC/TLM for an early stage evaluation
and verification at both hardware and software levels. The experimental results show that the
average ratios of computation cycles needed for non-blocking and blocking is 2 (burst mode) and
1.77 (single mode). In addition, we also used a high-level synthesis (HLS) tool to generate Verilog
RTL code of the communication unit to study the actual circuit timing and area.

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