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研究生: 鄭凱元
Kai-Yuan Cheng
論文名稱: 新型嵌入式一次性寫入記憶體元件
A Novel Embedded One Time Programming Memory
指導教授: 金雅琴
Ya-Chin King
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 55
中文關鍵詞: 內嵌式記憶體
外文關鍵詞: embedded, OTP, memory
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  • 在本研究中將提出一個全新的內嵌式非揮發性一次性寫入記憶體架構,本架構具有以下四個優點:第一:不需額外的製程及光罩,第二:高元件密度,第三:容易縮小,第四:低功率消耗。此內嵌式非揮發性一次性寫入記憶體為一N型的記憶體元件,利用保護層(Spacer)中的氮化層,作為儲存層,因此不須任何的額外製程及光罩,本元件利用汲極寫入(Source Side Injection)作為寫入的機制,可較有效率的將熱電子注入儲存層中。同時利用二維的製程及電性模擬軟體來分析元件的基本特性,以此驗證本元件的可行性。經實驗證明,本架構已可在90nm、0.13□m的邏輯製程中實現出來,且相對於傳統的內嵌式非揮發性一次性寫入記憶體在製作成本及元件縮小性上確實有相當大的改進及優勢。


    In this work, a novel embedded non-volatile one-time programmable (OTP) memory is proposed. The four major advantages of the novel structure are as follows. First, the novel structure is fully logic-compatible without extra masks. Second, the novel structure has very high cell density. Third, the structure has high scalability. Fourth, the power consumption of the novel structure is very low. The novel structure is an n-type memory cell which uses the nitride layer of the spacer as the storage layer. Therefore, neither additional mask nor process is needed for the novel structure. The programming mechanism is source side injection, which can inject charges to the storage layer more efficiently. In this work, the 2-dimension simulation software (tsuprem4) is used to observe the fundamental principle to prove the practicability of the novel structure. The experiment results show that the new structure can be realized in 90nm and 13□m logic CMOS process and compare to traditional one-time programmable memory cells, the novel structure has ascendancy and good improvement on cost and scalability.

    第一章 緒論 第二章 回顧與發展 第三章 元件架構及模擬 3.1 新型嵌入式一次性寫入記憶體元件結構 3.2 源極注入機制 3.3 新型一次性寫入非揮發性記憶體元件的寫入機制 3.4 模擬簡介 3.5 讀取電性模擬 3.6 電子注入點 3.7 編碼過程中注入點位置及強度的變化 3.5 等效電路 3.6 寫入閘極(PG)選擇閘極的耦合率(SG) 第四章 量測結果 4.1 元件讀取特性 4.2 讀取電壓最佳化 4.3 資料儲存性(Retention) 4.4 寫入干擾及讀取干擾 4.5 兩閘極距離的上下限(Spacing Window ) 4.6 寫入電流(Program Current) 4.7 寫入效率(Program Efficiency) 4.8 等效電路印證(Sub-circuit Verification) 4.9 掃描不同閘極所產生的I-V圖形變化 4.10 第二位元編碼(Second Bit Program )的讀取特性 4.11 單一元件儲存兩位元(Two Biter Cell)的讀取方式 4.12 閘極距離(Spacing)對元件的影響 4.13 紫外線抹除(UV Erase) 4.14 0.13um及90nm特性比較 第五章 結論 參考文獻

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