當金屬氧化物半導體技術的尺寸縮小至奈米(nano-scale)時，功率密度(power density)變成尺寸繼續縮小的關鍵。當功率密度達到每平方厘米數百瓦時候，電源干擾(power noise)將是如何設計可靠二維(2D)或者三維(3D)積體電路(IC)的嚴苛挑戰。為了滿足降低電源干擾的需求，我們提出三個關鍵新結構(architecture)。(1)第一個新積體電路結構是使用可重構造(reconfigurable)的工程變更(ECO)標準單元(standard cell)建立耦合電容器(decoupling capacitor)。這些可重新構造的耦合電容器將使用在電力網路(power network)中以降低因IR造成的電壓下降(IR drop)。第二個新積體電路結構是使用相對溫度感知器(relative temperature sensor)置放在熱點(hot spot)裡測量準確的溫度數據。在晶片設計過程中，這些相對溫度感知器被使用在熱點的動態熱源管理。第三個新積體電路結構是使用在3D IC的電力網路建造。這個新電力網路新結構透過使用3D IC的穿透矽通道(through-silicon-via: TSV)技術幫助解決靜態和動態的電壓下降(voltage drop)。

與傳統的工程變更設計流程比較下(10%的額外面積)，在使用工程變更設計流程之前，我們的方法顯示減少15%的IR壓降和9%漏電流。在使用工程變更設計流程之後，我們的方法顯示減少7%的IR壓降。此外，在使用我們最佳化的工程變更設計流程之後，由於產生較少的IR壓降與自由選擇任何標準工作單元，我們的方法顯示僅有非常少未解決的違反時序路徑(timing violation path)。

關於相對溫度感知器，與絕對溫度感知器相比較(其最大溫度誤差高達15℃)，我們的相對溫度感知器的最大溫度誤差只有6.5℃並減少69%的面積(如果使用1um寬的金屬連接線, 一個相對溫度感知器包含5個熱源(hot spot)專用電晶體 -HBJT);或者，我們的相對溫度感知器的最大溫度誤差只有5.4℃並增加3%的面積(如果使用10um寬的金屬連接線, 8 HBJTs)。

對於單一電壓域(single power domain)和多重電壓域(multiple power domain)，根據MCNC測試電路，我們提出的堆疊穿透矽通道分發網路-STDN (Stacked-TSV Distributed Network)顯示良好的3D佈置(floorplan)、IR壓降、電源干擾、溫度、使用面積和信號連接的總長度。

As feature size of MOS technology continues to shrink into nano-scale, power density becomes a critical issue for transistor scaling. When power density reaches hundreds of watt per centimeter square, power noise challenges 2D chips or even 3D chips to design a reliable IC. To meet the demand of power noise reduction, three new key architectures are proposed: (1) reconfigurable Engineering Change Order (ECO) cells used as decoupling capacitors to reduce voltage (IR) drop and as functional spare cells to solve timing closure; (2) relative temperature sensor to measure accurate temperature data in hot spots to help dynamic thermal management in chip design; (3) a new architecture for power network in three dimensional (3D) integrated circuit (IC) to solve static and dynamic voltage drop in through-silicon via (TSV) technology of 3D IC.

Compared with traditional ECO flow, our proposed reconfigurable ECO cell and its corresponding flow shows 15% reduction in maximum IR drop and 9% reduction in leakage before applying ECO, and 7% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, it shows that there are less unsolved timing-violation paths left after applying our proposed reconfigurable ECO timing optimization flow due to less IR drop and free selection of ECO gate type.

As to relative temperature sensor, compared with the absolute temperature sensor where maximum temperature error could be as high as 15℃, our relative temperature sensor shows 6.5℃ maximum temperature error with 69% area reduction using 1 um wide metal connection when 5 HBJTs (bipolar junction transistors placed at hot spots) are used in a cluster, and 5.4℃ maximum temperature error with 3% area overhead using 10 um wide metal connection when 8 HBJTs are used in a cluster, in the best case.

Both in single-power-domain and multiple-power-domain of the power network in 3D IC, our proposed STDN architecture demonstrates good performance in 3D floorplan, IR drop, power noise, temperature, area and even the total length of signal connections for selected MCNC benchmarks.

[1] Patrik Larsson, “Parasitic Resistance in an MOS Transistor Used as On-Chip Decoupling Capacitance,” IEEE Journal of Solid-State Circuits, vol. 32, no. 4, April 1997, pp. 574-576.
[2] Neil Weste and David Harris, “A circuits and Systems Perspective(3rd Edition),” Addison Wesley
[3] H. B. Bkoglu, “Circuits, Interconnections, and Packaging for VLSI,” Addison Wesley, 1990.
[4] “Benchmark Suite for International Test Conference 1999 (ITC99),” [Online]. Available: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.
[5] “Manual of SOC Encounter 2007,” http://www.cadence.com/.
[6] Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang, “ECO Timing Optimization Using Spare Cells,” International Conference on Computer Aided Design, 2007, pp. 530-535.
[7] S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran,and R. Panda, “Vectorless Analysis of Supply Noise Induced Delay Variation,” International Conference on Computer-Aided Design, 2003, pp. 184-190.
[8] Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang and Malgorzata Marek- Sadowska, “Engineering Change Using Spare Cells with Constant Insertion,” International Conference on Computer-Aided Design, 2007, pp. 544-547.
[9] Haihua Su, Sachin S. Sapatnekar and Sani R. Nassif, “An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts,” Proceedings of the International Symposium on Physical Design, 2002, pp.68-73.
[10] Chih-chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska and Kwang-Ting Cheng, “Logic Synthesis for Engineering Change,” Conference on Design Automation Conference, 1995, pp. 647-652.
[11] Sanjay Pant and David Blaauw, “Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks,” Conference on Design Automation Conference, 2007, pp. 757-762.
[12] Hang Li, Zhenyu Qi, Tan, S.X.D., Lifeng Wu, Yici Cai and Xianlong Hong, “Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization,” Conference on Design Automation Conference, 2005, pp. 170-175.
[13] “Study about Spare Cells,” [Online]. Available: http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells.
[14] Ying-Hao Ma, “Introduction to ECO Design Flow,” NCTU IC Lab, 2005.
[15] M. K. Gowan, L. L. Biro, and D. B. Jackson, “Power Considerations in the Design of the Alpha 21264 Microprocessor”, Proc. IEEE/ACM Des. Automat. Conf., 1998, pp. 726-731.
[16] Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh, “Decoupling Capacitance Allocaiton and Its Application to Power-Supply Noise-Aware Floorplanning,” IEEE Tran. on Computer-Aided Design of Integrated Circuits and System, Vol. 21, NO. 1, Jan. 2002, pp. 81-92.
[17] “Predictive Technology Model: 90nm, 65nm, 45nm BSIM4 model cards for BULK MOS,” [Online]. Available: http://www.eas.asu.edu/_ptm.
[18] H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez, “Thermal management system for high performance PowerPCTM microprocessors,” in COMPCON ’97: Proceedings of the 42nd IEEE International Computer Conference, 1997, pp. 325–330.
[19] R. Mukherjee and S. O. Memik, “Systematic temperature sensor allocation and placement for microprocessors,” in Proceedings of the 43rd conference on Design Automation, 2006, pp. 542–547.
[20] M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, “A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1℃ from -55℃ to 125℃,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2805–2815, dec 2005.
[21] D. E. Duarte, G. Taylor, K. L. Wong, U. Mughal, and G. Geannopoulos, “Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor,” in Proceedings of the 2007 international symposium on Low power electronics and design, 2007, pp. 304–309.
[22] A. Perrotin, D. Gloria, S. Danaie, F. Pourchon, and M. Laurens, “High frequency mismatch characterization on 170GHz HBT NPN bipolar device,” march 2006, pp. 169–172.
[23] M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” Solid-State Circuits, IEEE Journal of, vol. 24, no. 5, pp. 1433–1439, oct 1989.
[24] P. Drennan and C. McAndrew, “Understanding MOSFET mismatch for analog design,” Solid-State Circuits, IEEE Journal of, vol. 38, no. 3, pp. 450–456, mar 2003.
[25] “HSPICE Simulation and Analysis User Guide, V-2004.03,” Synopsys, 2004.
[26] “MPU interconnect technology requirements - near-term years,” in ITRS 2007 Edition: Interconnect, 2007.
[27] D. C. Burger and T. M. Austin, “The SimpleScalar tool set, version 2.0,” in Computer Architecture News, vol. 25, no. 3, 1997, pp. 13–25.
[28] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for architectural-level power analysis and optimizations,” in ISCA, 2000.
[29] W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “HotSpot: Thermal modeling for CMOS VLSI systems,” in IEEE Transactions on Component Packaging and Manufacturing Technology, 2005.
[30] L. J. Heyer, S. Kruglyak, and S. Yooseph, “Exploring expression data: identification and analysis of coexpressed genes,” vol. 9, no. 11, pp. 1106–1115, nov 1999.
[31] “SPEC-CPU2000, standard performance evaluation council, performance evaluation in the new millennium, version 1.1,” 2000. [Online]. Available: http://www.specbench.org/osg/cpu2000.
[32] W. Chen,W. R. Bottoms, K. Pressel, and J.Wolf, “The next step in assembly and packaging: System level integration in the package (SiP),” Tech. Rep., 2008.
[33] M. Umemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai, and K. Takahashi, “High-performance vertical interconnection for high-density 3D chip stacking package,” in Proc. Electronic Components and technology Conference ECTC, 2004, pp. 616–623.
[34] S. Sapatnekar, “Addressing thermal and power delivery bottlenecks in 3D circuits,” in Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, Jan. 2009, pp. 423–428.
[35] Y.-J. Lee, Y. J. Kim, G. Huang, M. Bakir, Y. Joshi, A. Fedorov, and S. K. Lim, “Co-design of signal, power, and thermal distribution networks for 3D ICs,” in Design, Automation Test in Europe Conference Exhibition, 2009. DATE ’09., Apr. 2009, pp. 610–615.
[36] P. Falkenstern, Y. Xie, Y.-W. Chang, and Y. Wang, “Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis,” in Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, Jan. 2010, pp. 169–174.
[37] G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. Meindl, “Power delivery for 3d chip stacks: Physical modeling and design implication,” in Electrical Performance of Electronic Packaging, 2007 IEEE, Oct. 2007, pp. 205 –208.
[38] Y. Guillou. (2009, Jun.) 3D integration for wireless products: An industrial perspective. [Online]. Available: http://www.i-micronews.com/analysis/3DIntegration-wireless-products-industrial-perspective,3272.html.
[39] M. Koyanagi, T. Fukushima, and T. Tanaka, “Three-dimensional integration technology and integrated systems,” in Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, Jan. 2009, pp. 409–415.
[40] W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “An ILP algorithm for postfloorplanning voltage-island generation considering power-network planning,” in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, Nov. 2007, pp. 650–655.
[41] H. Su, S. Sapatnekar, and S. Nassif, “Optimal decoupling capacitor sizing and placement for standard-cell layout designs,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, no. 4, pp. 428–436, Apr 2003.