由於二維材料天生具有原子等級的厚度，以及得天獨厚的物理特性，被視為下世代電子與光電元件的最有潛力的候選之一。然而，高接觸電阻是一項制約二維元件的重要因素，其超薄結構更是大幅提高接觸電阻改善工程的困難度。石墨烯被認為是一個良好的二維電極材料，根據文獻報導其與二硫化鉬、二硫化鎢的異質結構可以有效降低接觸電阻。然而以化學氣相沉積法成長的石墨烯與過渡金屬二硫族化物異質結構之中，目前發表的文獻僅限於N型場效電晶體的接觸電阻降低，缺乏P型通道的電晶體將嚴重限制二維互補式金屬氧化物半導體的發展。本論文旨在藉由化學氣相沉積法成長石墨烯與二硒化鎢平面異質結構，並進一步研製P型的場效電晶體。數層二硒化鎢與數層石墨烯在介面處垂直堆疊，大幅降低P型場效電晶體的接觸電阻，更值得注意的是，儘管有數層二硒化鎢在介面處，有效控制成長條件之下，電晶體的通道區域仍然只有單層的二硒化鎢。更進一步利用摻雜當作源極與汲極石墨烯的方式，電晶體的開關比可以有效提高兩個數量級，在一般大氣環境下量測值直逼十的八次方，同時，不管後續金屬電極所擁有的金屬功函數為何，此電晶體的P型單極性並不會被改變。在這裡，我們提出數層石墨烯作為二維版本的抬升式源極與汲極結構設計(raised source/drain，RSD)，探討下世代電子元件的發展可能性。

Two dimensional (2D) materials are drawing growing attention for next-generation electronics and optoelectronics owing to its atomic thin layer and unique physical properties. One of the challenges posed by 2D materials for transistor applications is the large source/drain (S/D) series resistance due to their thinness, which may be resolved by thickening the source and drain regions. Recently explored lateral graphene−MoS2 and graphene−WS2 heterostructures shed light on resolving this issue owing to their superior ohmic contact behaviors. However, recently only n-type field-effect transistors (FETs) are reported for transistors with graphene-TMD heterostructures. The lack of p-type transistor limits their applications in complementary metal-oxide semiconductor (CMOS) electronics. In this dissertation, we devote on demonstrating p-type FETs based on graphene-WSe2 lateral heterojunctions grown with the scalable CVD technique. Few-layer WSe2 is overlapped with the multilayer graphene (MLG) at MLG-WSe2 junctions such that the contact resistance is reduced drastically. Importantly, the few-layer WSe2 only forms at the junction region while the channel is still maintained as a WSe2 monolayer for transistors operation. Furthermore, by imposing doping to graphene S/D, two orders of magnitude enhancement in Ion/Ioff ratio to ~108 and the unipolar p-type characteristics are obtained regardless the work function of the metal in ambient air condition. The MLG is proposed to serve for a 2D version of emerging raised source/drain (RSD) approach in electronics.

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