整合扇出晶圓級晶片尺寸封裝 (InFO WLCSP) 是一項實現小晶片外型以及低製造成本的新興封裝技術，在整合扇出晶圓級晶片尺寸封裝中，作為接觸界面而無焊帽的銅 (Cu) 柱可以直接地被探測，因此降低了測試成本，但是無焊帽的銅柱暴露在空氣中的會逐漸地被氧化，而增加了接觸電阻並導致測試品質損失，為了緩解這問題，針戳是一種消除接觸表面氧化的方式，因此在業界中通常增加針戳的次數 (NTD)，能有效地處理氧化效應，也就是探測的更多次能夠幫助鑿穿氧化層，但是增加針戳的次數有可能會損壞待測裝置 (DUT)，所以針戳的次數要有個上限以防止良率損失，此外隨著針戳的次數增加，探針的針尖有較高的機會附著上氧化顆粒，從而增加了接觸電阻，為了緩解這個問題，磨針的針尖來除去氧化顆粒是種常用的機制，為了維持測試品質經常會提高磨針的次數 (NP)，但隨著磨針的次數提高，探測的時間會變長，而增加了測試成本，此外提高磨針的次數也會縮短探針的剩餘壽命。場位的數目 (NS) 代表多少 (晶粒) 可以同時地被一個探針卡探測以降低測試時間，雖然增加場位的數目可以降低測試時間，但是也會增加探針卡的成本，所以需要找出一個最佳的數值。因此很顯然為了降低探測的成本並且維持測試品質，應當提出一個以這些彼此互斥的參數構成的最佳化方法，在這項工作中我們發展出一個成本模型來分析成本對於針戳的次數、磨針的次數、場位的數目的關係，並藉由這個成本模型可以有效地找到具有經濟效益的探測配置及程序。由一個業界例子的實驗結果顯示在五個場位、針戳兩次、每探測三顆晶粒做一次磨針的配置下，測試成本可以被降低多達40.63%。

The integrated fan-out wafer level chip scale packaging (InFO WLCSP) is one of the emerging packaging technologies to achieving small chip form factor with low manufacturing cost. In InFO WLCSP, copper (Cu) pillars are used as the contact interfaces, which can be probed directly without solder caps, thus decreasing test cost. Without solder caps, however, Cu pillars that are exposed in the air will be oxidized gradually, which increases the contact resistance, and leads to test quality loss. To alleviate this problem, the touch-down is a scheme to remove oxidation which comes from contact interface. Thus, increasing the number of touch-downs (NTD) is usually used in the industry, which deals with oxidation effect efficiently, i.e., probing more times, can help penetrate the oxide layers. However, increasing NTD may damage the device under test (DUT), so there is a limit for NTD to prevent yield loss. Moreover, with an increased NTD, there is a higher chance for the probe tips to get attached by particles, and increases the contact resistance again. To alleviate this issue, polishing the tips to remove the attached particles is a commonly used mechanism. Increasing the number of polish (NP) is often adopted to maintain the test quality. As NP increases, however, a longer probing time is required, thus increasing the test cost. In addition, increasing NP shortens the remaining lifetime of probes. To reduce the test time, a number of sites (dies) can be concurrently tested by a probe card, which is denoted as NS. Increasing NS can reduce test time, but it also increases the probe card cost, so an optimal value needs to be identified. It therefore is clear that an optimization methodology should be developed, based on these competing parameters, in order to reduce the probing cost while maintaining the test quality. In this work, we develop a cost model to analyze the cost with respect to NTD, NP, and NS. With the proposed cost model, cost-effective probing configurations and procedures can be found effectively. Experimental results from an industrial case show that as much as 40.63% of the cost can be saved with NS = 5, NTD = 2, and the probe tips are polished after every 3 dies are probed.

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