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研究生： 譚杰城
Tam, Kit-Seng
論文名稱： 一種可以保證錯誤率的有效率近似節點合併的研究
An Efficient Approximate Node Merging with an Error Rate Guarantee
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 江介宏
Jiang, Jie-Hong
黃俊達
Huang, Juinn-Dar
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 25
中文關鍵詞： 邏輯合成 、近似計算
外文關鍵詞： Node Merging, Approximate Logic Synthesis
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    • 近似計算為針對可容忍錯誤之應用的新興設計範例，這類的應用如訊數處理、機器學習.......等。在近似計算中，可以通過換取電路的準確性來改善近似電路的面積、延遲或功耗。我們將於此論文提出一種基於節點合併技術並具有錯誤率保證的近似邏輯合成方法。提出之方法的想法是用定值替換電路中的點，並合併電路中功能相似的兩個節點。我們在IWLS2005和MCNC的電路上進行實驗，實驗結果顯示我們提出的方法能夠減少多達80%的面積，平均減少31%的面積。與最新的方法相比，我們提出的方法在相同的5%錯誤率限制下具有51倍的加速。

    Approximate computing is an emerging design paradigm for error-tolerant applications. e.g., signal processing and machine learning. In approximate computing, the area, delay, or power consumption of an approximate circuit can be improved by trading off its accuracy. In this paper, we propose an approximate logic synthesis approach based on a node-merging technique with an error rate guarantee. The ideas of our approach are to replace internal nodes by constant values and to merge two similar nodes in the circuit in terms of functionality. We conduct experiments on a set of IWLS 2005 and MCNC benchmarks. The experimental results show that our approach can reduce area by up to 80%, and 31% on average. Compared with the state-of-the-art method, our approach has a speedup of 51 under the same 5% error rate constraint.

    中文摘要 i Abstract ii 誌謝辭 iii Contents iv List of Tables vi List of Figures vii 1 Introduction 1 2 Preliminaries 3 2.1 Error Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 Node-Merging Approach . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Proposed Approach 7 3.1 Node to Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Node Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Error Rate Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Experimental Results 16 4.1 Probability p in Node to Constant Phase . . . . . . . . . . . . . . . . 16 4.2 Circuit Size Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Conclusion 21 6 Acknowledgement 22

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