這份論文研究了快閃記憶體在高次位元儲存應用下的訊號處理與低密度查核碼解碼架構。

首先介紹快閃記憶體的基本操作原理以及在使用過程中所遭受的儲存電荷偏移以及永固測試後的資料錯誤原因。闡述因為半導體製程微縮而引發快閃記憶體在傳統2D製程上的微縮極限，快閃記憶體的製程發展進而全面轉入3D立體結構。除此之外，為了更高容量的儲存密度，單一記憶體單元所儲存的位元數也增加到三位元或甚至是四位元。對應的儲存電荷位階也由八個位階增加一倍到了十六個位階。當3D快記憶體的堆疊結構增加時，除了單晶片的儲存容量倍數增加，但是也對應增加了許多設計的挑戰。接著介紹快閃記憶體中有關讀取資料的電路設計。從單位元開始到一個三位元的單元讀取過程，為了得到更強大的更正能力而使用軟式解碼的過程中需要讀取資料位元外還需要搭配其可靠度位元。

接下來呈現一個適合使用於高位元快閃記憶體的低密度查核碼的檢查矩陣設計。該設計擁有高碼率以及適合高速積體電路設計之特性。介紹重組信度傳遞解碼演算法在此檢查矩陣的結構下，使用降低記憶體存取頻寬的方法降低解碼器設計的複雜度。為了探討錯誤更正碼與快閃記憶體通道雜訊的整合設計。我們設計了一個有效模擬快閃記憶體通道雜訊的方法。利用此通道雜訊模擬，設計物理單元資料放置模式的方法來將儲存資料寫入快閃記憶的的單元中。抗雜訊能力勝於傳統的邏輯頁放置模式。探討在此通道雜訊下模擬低密度查核碼的軟式解碼方法及最佳化的更正力。

再來是為了增加高位元快閃記憶體的資料讀取效率我們提出了一個可能的讀取方法。藉由一個全域的讀取電壓掃描，直接紀錄該電荷準位。在設計一個新式的資料傳輸介面，將記錄下來的電荷準位分為符號位元傳輸與軟式位元傳輸。此訊號讀取方法洽可以與所提出的快閃記憶體雜訊模型吻合。在解碼端收取符號位元與軟式位元計算每一個資料位元的可靠度再進入低密度查核碼的軟式解碼。此方法可以提供更有效率且更正能力更強的解碼效果。

在論文的最後一部份提出了一個新穎的整合式方法。將先前所探討的所有方式結合用於真實快閃記憶體使用場景。此過程中包含的準位從新判定，軟式解碼可靠度映射，軟式解碼，決策回饋更新通道訊息，最少耗電下解碼成功。包含電荷準位偏移以及噪聲容限減少等狀況，都可以藉由單一讀取單一整體狀態傳輸，就可以一次將資料解碼成功。

This dissertation describes a data acquisition study the flash memory on the high level per cell applications by using Digial signal processing and the low desity parity check code(LDPC) decoding methods.

First, the NAND flash basic operaions and the data error behaviors from the endurance and data-retention disturbance will be introduced. Because of the 2D NAND flash's process shrinking limitation, the NAND flash process and structure move into 3D era from this year entirely. The single cell's stored bit number also increased from 3bit to 4bit and its number of levels were also improved from 8 to 16 levels. When increasing the stack number of the 3D structure, single chip storage capacity will become double in every generation, and there will be more design challenges . We introduced the data read flow and related circuit from single-level-cell(SLC) to tripple-level-cell(TLC) in the NAND flash. Except the data-bit access, the soft information fetching flow for the reliablity bit is needed for the stronger correction capability with the soft decoding.

Second, we showed a LDPC's parity check matrix(CPM) design which is suitable for the high level cell NAND flash. The CPM with high code rate is suitable for high throughput decoder's VLSI design. A shuffled message passing-decoding (MPD) was used in the PCM with a proposed memory access reduction method to reduce the design complexity. For the purpose of integrated design of the error correction code with the NAND flash channel model, we provided an efficient model to simulate NAND flash channel noise. According to this model, the physical cell based data allocation contributed a better noise immunity capability than the traditional logical page based(LPB) data placement. Then, we discussed the result from the LDPC soft-decoding and its optimization method for strogner correction capability from this noise model.

Third, we proposed a state-info sensing scheme for the improving of the high level cell NAND flash data access efficiency. This method recorded the state informaiton of the electron levels through a whole sensing range scan. We designed a new data transfer interface to deliever sign bit and the soft bit information sequentially. This single access method matched the proposed noise model. The decoder can identify each data-bit's LLR value from the sign bit and soft bit for the LDPC soft decoding. This method provided a more efficient and stronger correction capability.

In the last part of the dissertation, a systematic solution to utilize state-info sensing scheme for the real sitiuation. The whole process included new level identification, reliablility mapping, soft-decoding, decision feedback channel information reconstruction, and the minimum power for correctable decoding. The Vth-shifting and noise margin reduction cannot be solved by tradtional interface and method, but the proposed flow will get a successful decoding within a single read and one pass state information delivery.

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