在現今的系統級晶片(System on Chip, SoC)、動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）以及其它時間相關之電路設計中，『延遲鎖定迴路』(Delay-Locked-Loop, DLL) 被大量且廣泛的使用於消除時脈訊號產生的歪斜現象並使其隨時保持同步狀態。而在供應電壓越來越低以減少功率消耗的先進製程中，『全數位延遲鎖定迴路』(All-Digital-Delay-Locked-Loop, ADDLL) 有日漸取代傳統類比延遲鎖定迴路的趨勢。在前一項作品之中[9]，我們提出了一個可以快速且方便的產生一個『全數位相位鎖定迴路』(All-Digital-Phase-Locked-Loop, ADPLL)的自動產生器，它可以幫助使用者節省非常大量的設計時間與精力，同時也可簡易快速的在不同製程之間做轉換。我們在這篇論文中提出了一個由參數化的並聯架構延遲線段(Delay line)做為主體所構成之全數位延遲鎖定迴路，其架構不僅可以提供非常小的延遲線段解析度，同時也可以達到寬闊的可調整延遲範圍區間。另外，基於減少設計上所消耗的精力時間這一相同的目標與概念下，我們更進一步提出了一個全數位延遲鎖定迴路自動產生器，它不僅可以快速且方便的產生一個符合使用者規格的全數位延遲鎖定迴路，也可經過簡易步驟後支援不同的製程。透過電晶體層級的模擬驗證，由我們的自動產生器所產生之全數位延遲鎖定迴路可以在台積電九零奈米製程下支援50MHz到1.25GHz的單頻時脈速度操作，在台積電一八零奈米製程下可支援50MHz到1GHz的單頻時脈速度操作。

Delay-Locked-Loop (DLL) is widely used in today’s System on Chip (SoC), DRAM interfaces or other timing circuits. Conventional analog DLLs can achieve better performance in jitter and skew, but nowadays digital DLLs becomes a better choice than analog DLLs. Our previous work in [9] proposed an ADPLL compiler for the use in timing-related circuit designs and has been widely used. In this work, we proposed a cell-based architecture of delay line for our all-digital DLL (ADDLL) circuit, which can provide small resolution and wide tuning range to meet the user’s demand. Moreover, we propose an ADDLL compiler which can not only generate an ADDLL circuit more easily and conveniently than a typical manual design, but also support easy process migration, saving a large amount of design effort. The transistor level simulation results show that this compiler can provide single clock frequency operation from 50MHz to 1.25GHz in TSMC90 process and 50MHz to 1GHz in TSMC18 process.

[1]S.-L. Chen, M.-J. Ho, Y.-M. Sun, M.-W. Lin, and J.-C. Lai, “An All-Digital Delay-Locked Loop for High-Speed Memory Interface Applications,” in Proc. VLSI Design, Automation and Test (VLSI-DAT), 2014.

[2]Y.-H. Tu, K.-H. Cheng, H.-Y. Wei, and H.-Y. Huang, “A Low Jitter Delay-Locked-Loop Applied for DDR4”, in Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013.

[3]J.-Y. Liu, S.-Y. Huang, and T.-S. Chu, "Cell-Based Programmable Phase-Shifter Design for Pulsed Radar SoC", in Proc. of IEEE Int'l Conf. on ASIC, Nov. 2015. (invited)

[4]T. Olsson and P. Nilsson, “A fully integrated standard-cell digital PLL,” IEE Electron. Lett., vol. 37, pp. 211–212, Feb. 2001.

[5]T. Olsson and P. Nilsson, “A Digitally Controlled PLL for SoC Applications,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, MAY. 2004.

[6]Y.-W. Chen and H.-C. Hong, “A Fast-Locking All-Digital Phase Locked Loop in 90nm CMOS for Gigascale Systems,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2014.

[7]J.-A. Tierno, A.-V. Rylyakov, and D.-J. Friedman, “A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI,” in IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 42–51, 2008.

[8]Y.-J. Liao and S.-Y. Huang, "Temperature Tracking Scheme for Programmable Phase-Shifter in Pulsed Radar SoC", in Proc. of IEEE Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2016. (accepted for publication).

[9]C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, Mar. 2014.

[10]C.-C. Chung and C.-Y Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 347–351, Feb. 2003.

[11]K. Arshak, O. Abubaker, and E. Jafer, “Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed and low jitter PLL,” in IEEE International Caracas Conference on Devices, Circuits and Systems, Vol. 1, pp. 188-191, Nov. 2004.

[12]Y.-P. Zhou, Z.-Q. Lu and Y.-Z. Ye, “A Double-Edge-Triggered Phase Frequency Detector for Low Jitter PLL,” in Proc. International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.1963-1965, Oct. 2006.

[13]W.-J. Yun, et al., ”A 0.1-to-1.5GHz 4.2mw All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 282-283, 2008.

[14]M.-H. Hsieh, L.-H. Chen, S.-I. Liu, and C. C.-P. Chen, “A 6.7MHz-to-1.24GHz 0.0318〖mm〗^2 Fast-Locking All-Digital DLL in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 244-245, 2012.

[15]Y.-S. Kim, S.-K. Lee, H.-J. Park and J.-Y. Sim, “A 110 MHz to 1.4GHz Locking 40-Phase All-Digital DLL,” IEEE J. Solid-State Circuits, vol. 46, no. 2, Feb. 2011.

[16]L. Wang, L. Liu, and H. Chen, “An Implementation of Fast-Locking and Wide Range 11-bit Reversible SAR DLL,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 57, no. 6, pp. 421-425, Jun. 2010.

[17]C.-Y. Yao, Y.-H. Ho, Y.-Y. Chiu, and R.-J. Yang, “Design a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line,” IEEE Trans. On Very Large Scale Intergration Systems, vol. 23, no. 3, pp. 567-574, Mar. 2015.

[18]H.-H. Chang, and S.-I. Liu, “A Wide Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661-670, Mar. 2005.