隨著製程不斷演進，電源電壓降（IR-drop）已經成為設計晶片的重要考量之一。若電流供應網路布局設計不夠完整，當大量局部的標準元件瞬間信號改變，將會造成當地的電流需求增大，若此時電流供應不足，將會造成嚴重的電源電壓降問題。而這個現象可能會對晶片的可靠度造成相當程度的影響。在傳統的晶片設計流程中，當我們在繞線過後發現其晶片有電源電壓降問題，因為此時的晶片布局中已經存在時脈樹、信號布線、標準原件以及其接腳，這會使得我們很難找到一個連續且足夠寬敞的空間來加粗既有的電源訊號或是擺置新的電源訊號使得電源供應網路密度得以提高。在這個情況下，一般來說將會捨棄目前的布局設計，回到設計電源供應網路，而這將會造成額外的時間消耗。
在這篇論文中，為了避免重新設計晶片布局所造成的巨大成本，我們提出一個布線過後針對動態電源電壓降進行電源供應網路修補的辦法，藉由商業布局與繞線軟體來實現。並且使用梯度下降演算法來計算較有效率的修補路徑，由此路徑來決定其修補區域。利用所剩的繞線資源，透過不規則形狀之電源信號來補強既有的電源供應網路。我們使用台積電90奈米製程來實現ITC’99基準晶片進行實驗，實驗結果指出，我們所提出的補強電源供應網路之方法可以在信號繞線後將最差的動態電源電壓降從原本的15.50％降低到8.79％，也就是43.29％的改善。

With the rapid evolution of technology, IR-drop has become a major concern in current VLSI designs. An insufficient construction of power distribution network (PDN) leads to severe voltage (IR) drop, because of localized logic cells switching and the PDN may not be enough to support the current demand in the IR-drop hot spot. This problem may affect the performance of the chip seriously. In a conventional integrated circuit (IC) design flow, once a post-route design violates the IR-drop constraint, the design is usually discarded, we should redesign the PDN by iterating back to earlier stages, because traditional repair methods, such as power stripe widening and insertion, are unlikely to succeed due to routing congestion in post-route stage. It may take extra unpredictable turnaround time. In order to avoid the great costs of redesigning the chip, an engineering change order (ECO) approach to mitigate the IR-drop at the post-route stage by the commercial automatic P&R tool, is preferred. In this work, the gradient descent algorithm is used to select the regions that require reinforcement by using ECO power wires that have a detour-shape. We utilize the remaining white space to enhance the PDN. The experimental results on a test set of ITC'99 benchmark circuits show that, in the post-route stage, the worst-case dynamic IR-drop can be mitigated by our ECO approach from 15.50% to 8.79%. That is to say, the improvements of dynamic IR-drop is 43.29%.

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