操作於 2.4 GHz 之數位頻率轉換器｜國立清華大學博碩士論文庫

簡易檢索 / 詳目顯示

回結果列表

研究生：	章晉祥 Ching-Hsiang Chang
論文名稱：	操作於 2.4 GHz 之數位頻率轉換器 A 2.4-GHz Digital-to-Frequency Converter
指導教授：	柏振球 Jenn-Chyou Bor
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	99
中文關鍵詞：	數位頻率轉換器、頻率合成器
外文關鍵詞：	digital-to-frequency converter, frequency synthesizer
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文主題為設計一個符合2.4-GHz之工業/科學/醫療頻段之應用的數位頻率轉換器(DFC)。數位頻率轉換器是直接將輸入的數位頻率控制碼轉換成週期性的類比訊號輸出，使得輸出類比訊號的頻率與輸入數位控制碼的數值有正比的關係。由於不採用回授控制迴路而直接採用開路控制，此數位頻率轉換器可達到相當快速的頻率切換，對於某些無線應用，像是高傳輸速率之頻率調變無線發射器來說，這是十分重要且不容忽視的。
提出的設計架構包含了一個數位控制震盪器(DCO)、一個高速閘控漣波計數器以及一個數位控制電路用來校準電容以及頻率。使用數位控制震盪器做為基礎，可避免吵雜的類比控制，進而達到穩定且精準的頻率訊號輸出。數位到頻率的轉換是利用建立一個輸入頻率數位碼對數位控制震盪器控制碼的對照表來實現。考慮到硬體的複雜度以及製程變異，提出兩個演算法分別採用片段式線性近似法以及非二進制權重的切換電容陣列來達成轉換輸出頻率的最小誤差。
此設計利用台灣積體電路公司的互補式金氧(CMOS) 0.18微米製程實現，整個晶片面積為1 x 1 平方微米。經由量測結果，震盪頻率輸出範圍為2.34 ~ 2.59 GHz，相位雜訊在偏離中心載波頻率500 KHz低於-102 dBc/Hz。有效頻率解析度為7位元，且在供應電壓為1.8伏特的情形下，功率消耗為13微瓦特。

In this thesis, a digital-to-frequency converter (DFC) designed for 2.4 GHz ISM-band applications is proposed. The DFC directly produces an analog periodic output signal which frequency is proportional to the input digital code. Since there is no feedback control loop, the converter can achieve very fast frequency-switching which is important for some wireless applications, for example: high data-rate FSK transmitters.

The proposed design consists of a digitally controlled oscillator (DCO), a high speed gated ripple counter, and a digital control circuit for capacitance and frequency calibration. The DCO-based design provides stable and precise output frequency by avoiding noisy analog control. The digital-to-frequency conversion is realized by transfer the input frequency code to the capacitor control code of the DCO. Considering hardware complexity and process variations, two transfer algorithms for piecewise linear approximation and non-binary-weighted switched-capacitor arrays are proposed to minimize output frequency error.

This design is implemented in TSMC 0.18 µm 1P6M CMOS process and the chip area is 1 x 1 mm2. According to the measurement results, the oscillation frequency is 2.34 ~ 2.59 GHz with 255 MHz tuning range, and the phase noise is less than -102 dBc/Hz at 500 kHz offset. The effective frequency resolution is 7 bits and the total power consumption is 13 mW under 1.8 V supply voltage.

Chapter 1     Introduction                                            1
1.1    Background                                                    1
1.2    Motivation                                                        2
1.3    Thesis Organization                                                5

Chapter 2    Digital-to-Frequency Converter Architecture and Design Concept                                                7
    2.1 Introduction                                                    7
    2.2 Digital-to-Frequency Converter Design Specification                    9
        2.2.1 Frequency Tuning Range and Resolution                        9
        2.2.2 Frequency Accuracy                                       10
        2.2.3 Phase Noise                                               13
        2.2.4 Proposed Digital-to-Frequency Converter Specification           15
    2.3 Digital-to-Frequency Converter Design Architecture                   16
        2.3.1 Digitally Controlled Oscillator                               16
        2.3.2 Gated Ripple Counter                                       18
        2.3.3 Digital Control Circuit                                       21
    2.4 Digital-to-Frequency Converter Design Concept                       21
        2.4.1 Accurate Tuning Capacitor                                   22
        2.4.2 Frequency to Capacitance Transfer                           23
    2.5 Digital-to-Frequency Converter Operation Timing Control               25
    2.6 Summary                                                       26

Chapter 3    Digitally Controlled Oscillator and Gated Ripple Counter Design                                          27
    3.1 Digitally Controlled LC Oscillator Design                           27
        3.1.1 Basic of LC Oscillator                                       27
        3.1.2 Negative Resistance Circuit                                   31
        3.1.3 Switched-Capacitor Array and Digital Control Buffer               33
        3.1.4 TSMC Spiral Inductor                                       37
        3.1.5 Output Buffer and Full-Swing Buffer                           38
        3.1.6 Simulation Result                                           41
    3.2 Gated Ripple Counter Design                                       45
        3.2.1 AND Gate                                               45
        3.2.2 Ripple Counter                                           46
        3.2.3 Simulation Result                                           48
    3.3 Summary                                                       50

Chapter 4    Digital Control Circuit Design                          52
4.1 Frequency Detection                                               52
    4.2 Accurate Tuning Capacitor Design                                   56
        4.2.1 Non-binary-weighted Tuning Capacitor Array Design               57
        4.2.2 Binary to Non-binary Transfer                               59
        4.2.3 Non-binary-weighted DCO Capacitor Control Code Calibration       62
    4.3 Frequency to Capacitance Transfer Design                           67
        4.3.1 Piecewise Linear Approximation                               67
        4.3.2 Segment Frequencies Calibration                               69
        4.3.3 Approximation Error Analysis                               70
    4.4 Summary                                                       72

Chapter 5     Digital-to-Frequency Converter Simulation and Measurement Result                                  73
    5.1 Digital-to-Frequency Converter Integration                           73
        5.1.1 Behavior Simulation                                       73
        5.1.2 Layout Consideration                                       76
    5.2 Chip Measurement Result                                           77
        5.2.1 Measurement Setup                                       77
        5.2.2 Measurement Result                                       80
        5.2.3 Measurement Discussion                                   92
    5.3 Summary                                                       94

Chapter 6    Conclusion and Future Work                          95
    6.1 Conclusion                                                   95
    6.2 Future Work                                                   96

Reference

                                

[1] Robert Bogdan Staszewski, John L. Wallberg, Sameh Rezeq, Chih-Ming Hung, Oren E. Eliezer, Sudheer K. Vemulapalli, Chan Fernando, Ken Maggio, Roman Staszewski, Nathen Barton, Meng-Chang Lee, Patrick Cruise, Mitch Entezari, Khurram Muhammad, and Dirk Leipold, “All-digital PLL and transmitter for mobile phones”, IEEE Journal of Solid-State Cicuits, Vol. 40, Dec. 2005, pp. 2469-2482
[2] Robert Bogdan Staszewski and Poras T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS”, John Wiley and Sons, INC., New Jersey, 2006
[3] Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, and Poras T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process”, IEEE Trans of Circuits and Systems II, Vol. 50, Nov. 2003, pp. 815-828
[4] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A portable digitally controlled oscillator using novel varactors”, IEEE Trans of Circuits and Systems II, Vol. 52, May 2005, pp. 233-237
[5] Robert Bogdan Staszewski, Chih-Ming Hung, Dirk Leipold, and Poras T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications”, IEEE Trans on Microwave Theory and Techniques, Vol. 51, Nov 2003, pp.2154-2164
[6] Jianhua Gan and Jacob Abraham, “A non-binary capacitor array calibration circuit with 22-bit accuracy in successive approximation analog-to-digital converters”, IEEE MWSCAS, Vol. 1, Aug. 2002, pp. 567-570
[7] Robert Bogdan Staszewski, Dirk Leipold, and Poras T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation” , IEEE Trans of Circuits and Systems II, Vol. 50, Nov. 2003, pp. 887-892
[8] Jenn-Chyou Bor, “CMOS transfer gate and dynamic logic”, lecture notes of Introduction to Integrate Circuits Design, Nov 2007
[9] Jianhua Gan, Joel Page, and Jacob Abraham, “Mixed-signal micro-controller for non-binary capacitor array calibration in data converter”, IEEE ACSSC, Vol. 2, Nov. 2002, pp. 1046-1049
[10] Jianhua Gan, Shouli Yan , and Jacob Abraham, “Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter”, IEEE ASP-DAC, Jan. 2004, pp. 292-297
[11] Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu (Andy) Wu, “A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time”, IEEE ISCAS, May 2006, pp. 4082-4085
[12] Robert Bogdan Staszewski, Dirk Leipold, John Wallberg, and Poras T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator”, IEEE CICC, Sept. 2003, pp. 571-574
[13] Rober Bogdan Staszewski, Chih-Ming Hung, Nathen Barton, Meng-Chang Lee, and Dirk Leipold, “A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones”, IEEE JSSC, Vol. 40, Nov. 2005, pp. 2203-2211

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文