傳統單層式儲存架構之NAND快閃記憶體多使用Hamming或是BCH碼等硬式決策技術來減緩因記憶格的錯誤而造成的影響，但由於電路越做越小的趨勢，隨著製程的逐漸縮小以及多層式儲存的技術的發展下，這些硬式決策技術的效能也地逐漸變差，以至於需要更強力的錯誤更正的方法來改善其效能，而低密度奇偶檢查碼即是一種擁有不錯的錯誤更正效能的軟式決策技術。在NAND快閃記憶體的應用上，高碼率和低成本的解碼器是不可或缺的。不規則的(18624, 16704)和(18432, 16704)碼率分別為0.896和0.906的準循環低密度奇偶檢查碼被用於本作中。我們以兩層式編碼器和一種低成本解碼架構來呈現應用於NAND快閃記憶體的低複雜度奇偶檢查碼的編解碼器。除此之外，編碼器-解碼器的共用得以降低實作複雜度。最後我們提出一種用於解碼器的低複雜度的檢查節點單元在不影響錯誤更正效能的前提下來最佳化檢查至變數節點訊息以降低儲存複雜度。此低密度奇偶檢查碼之編解碼器以TSMC 90奈米技術實現，在操作頻率166 MHz下編碼器可以達到4.03 Gb/s同時解碼器可以達到2.35 Gb/s的吞吐量。

Conventional NAND Flash memory with single-level cell architecture is implemented in hard-decision techniques such as Hamming or BCH codes to mitigate the effect of memory cell errors. However, it needs much more powerful error correction technique as these hard-decision techniques are not sufficient for multilevel technique and continuously scaled down cell size gradually. Low-density parity-check(LDPC) codes is a soft-decision technique with splendid error-rate performance. For NAND Flash applications, high-rate and low-cost decoders are required. Irregular (18624, 16704) and (18432, 16704) Quasi-Cyclic LDPC (QC-LDPC) code that has a code rate of 0.896 and 0.906 is used respectively. We presented a low-complexity LDPC Codec for NAND Flash implemented in two-stage encoder and a low-cost decoding architecture. In addition, encoder-decoder sharing is also implemented to reduce implementation complexity. Finally, we proposed a low-complexity check-node unit for decoder to optimize check-to-variable message to reduce storage complexity without error-rate performance loss. The LDPC Codec is implemented in TSMC 90-nm CMOS technology and the Two-Stage Encoder and the Decoder can achieve a throughput of 4.03Gb/s and throughput of 2.35Gb/s respectively at a clock frequency 166 MHz.

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