在這科技發達的時代，快閃記憶體元件已經充斥在我們生活當中，廣泛地應用在智慧型手機、平板電腦等可攜式電子產品上。傳統浮動閘極式快閃記憶體元件由於其結構的限制，已經無法滿足微縮發展的趨勢，因此電荷陷阱式快閃記憶體元件便取代了浮動閘極式快閃記憶體元件，成為未來發展的趨勢。然而當電荷陷阱式快閃記憶體元件微縮到次微米以下時，就無法再以降低穿隧氧化層厚度來提升元件的操作效率，所以就發展出取多改良的方法，例如能帶工程元件、奈米線通道結構元件。
在第一個實驗中，元件的電荷捕捉層分為單層氮化矽、二氧化鉿/氮化矽堆疊兩種，元件結構上則分為平面式與奈米線通道式。由於奈米線通道邊角的電場增強效應，因此奈米線通道式元件擁有較好的寫抹速度，而電荷捕捉層使用二氧化鉿/氮化矽堆疊的元件，在寫抹速度與電荷保持力上表現較好，並具有不差的耐久力特性。
在第二個實驗中，我們在元件的電荷捕捉層使用了三種堆疊：二氧化鉿/氮化矽、二氧化鉿/多矽型氮化矽、二氧化鉿/氮氧化矽/多矽型氮化矽，目的是透過調變氮化矽的比例以及多層堆疊來達到能帶工程的效果，電荷捕捉層使用二氧化鉿/二氧化矽/多矽型氮化矽堆疊的元件相比於其他兩種電荷捕捉層的元件，在寫抹速度上的表現相差不遠，但在電荷保持力以及耐久力方面則有改善。
在第三個實驗中，我們嘗試將二氧化鉿/多矽型氮化矽、二氧化鉿/氮氧化矽/多矽型氮化矽這兩種電荷捕捉層，製作在無接面奈米線通道結構的元件上，並與電荷反轉式奈米線通道結構的元件做比較，在寫抹速度方面，兩種結構表現相近，但在電荷保持力以及耐久力的特性上，無接面奈米線通道結構的元件則表現出較好的特性。
在第四個實驗中，想法是從改變元件結構下手，研究出3-D堆疊的元件來達到微縮的目的。元件設計成上下兩層，上下各有一對源極和汲極，使用一個共同閘極去控制兩個元件。希望藉此元件結構去觀察不同元件設計對電性干擾的影響。本次實驗的元件雖然無法運作，但透過一次完整的製程經驗，已證明此光罩與製程是確實可行的，只要將造成失敗的細節加以改善，相信是可以製作出可堆疊式垂直閘極的快閃記憶體元件。目前的元件結構設計只有兩層，但只要繼續研究，在日後製程穩定時，便可將其繼續往上堆疊，使得微縮元件的效果更好。

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