32通道即時且可擴增式神經動作電位分類演算法之硬體實現

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研究生：	馬婕芸 Ma, Jie-Yun
論文名稱：	32通道即時且可擴增式神經動作電位分類演算法之硬體實現 Scalable 32-channel Hardware Implementation of Real-time Spike Sorting Algorithm
指導教授：	陳新 Chen, Hsin 張彌彰 Chang, Mi-Chang
口試委員:	吳玉威 Wu, Yu-Wei 黃朝宗 Huang, Chao-Tsung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2022
畢業學年度：	111
語文別：	英文
論文頁數：	53
中文關鍵詞：	動作電位分類、特徵擷取、動作電位偵測、非線性能量運算子、離散小波轉換、K-means分群法、特殊應用積體電路、現場可程式化邏輯閘陣列
外文關鍵詞：	Spike Sorting, Feature Extraction, Spike Detection, Nonlinear Energy Operator (NEO), Discrete Wavelet Transform (DWT), K-means Clustering, ASIC, FPGA
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神經疾病是指影響神經系統的任何醫學病症，其治療方法相當廣泛。其中一種療法 – 腦深層電刺激術 (deep brain stimulation, DBS)，是一種利用手術將電極植入腦中並利用電脈衝調控異常神經電活動，達到減輕或控制症狀的技術。在神經系統中，動作電位 (action potentials, APs, or spikes) 在神經傳導的過程中扮演很重要的角色，且其波形會因為由不同神經產生而有變化。神經動作電位分類(spike sorting) 就是利用動作電位的波形，在一群神經元及神經雜訊中分出具有異常訊號的特定神經元，其動作電位的波形則是由電極紀錄而得。
在近幾年，許多先進的神經紀錄系統，其內建具有神經動作電位分類的演算法，但隨著越來越多高密度電極陣列 (high-density multi-electrode array devices, HD-MEA) 的的實作及發表，傳統的神經動作電位分類演算法已經不足以處理多通道的神經訊號。
因此，在本篇論文中有提出 32 通道即時神經動作電位分類的演算法，此演算法與絕大多數動作電位分類的處理方法相似，包含偵測動作電位、取出特徵值以及分類。其中有使用到非線性能量運算子 (nonlinear energy operator, NEO)、離散小波轉換 (discrete wavelet transform, DWT) 以及 k-means 分群 (k-means clustering)。這些步驟利用單通道神經數據模擬資料庫、多通道神經紀錄數據及開源的神經動作電位分類工具 (KiloSort 2.0) 來做驗證。提出的演算法能夠即時的處理32 通道的細胞外神經資訊，在偵測動作電位中可達到88.22%的真陽率 (true positive rate, TPR)，且能夠分出 33 個好的神經單位。
除此之外，在論文中也實作了 32 通道即時神經動作電位分類系統在現場可程式化邏輯門陣列 (field-programmable gate array, FPGA) 與特殊應用積體電路 (application specific integrated circuit, ASIC)上。透過合成結果，在有限的運算資源、系統功率、面積、擴增性、和演算法的正確率上的取捨能夠被量化，能夠讓設計者在設計初期有依據的決定其多通道動作電位分類系統是否可行。

Neurological disorder is referred to any disorder of the nervous system. Deep brain stimulation (DBS) is a surgical procedure used to treat its symptoms. In a nervous system, action potentials (APs, or spikes), play a central role in communication among neurons, and they have different shapes. Spike sorting then takes advantage of the shapes of waveforms collected by electrodes to distinguish the abnormal activities of the targeted neurons from other neurons and from background electrical noises.
In recent years, there have been several advanced neural recording systems embedded with spike sorting algorithms. However, with newly published high-density multi-electrode array devices (HD-MEA), the traditional spike sorting algorithm becomes inadequate to process multi-channel neural data.
As a result, a 32-channel real-time spike sorting algorithm is proposed in this thesis. The algorithm follows the classic spike sorting procedure, including spike detection, feature extraction and clustering. In these steps, nonlinear energy operator (NEO), discrete wavelet transform (DWT) and k-means clustering algorithm are applied. These methods are validated by published single-channel simulated datasets, neural recording multi-channel data, and open-source spike sorting tool, KiloSort2.0. The proposed algorithm is able to process 32-channel extracellular neural data, detect spikes with 88% true positive rate, and identify 33 good units in real time.
Also, 32-channel real-time spike sorting systems based on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) are presented. With the synthesis results from both implementations, the trade-off between computational resources, system power, area, scalability, and accuracy of algorithm becomes measurable. And it provides insight into whether a high-channel-count spike sorting system is feasible or not in the preliminary design stage.

摘要...................................................................................i
Abstract...............................................................................ii
致謝...................................................................................iii
List of Content........................................................................iv
List of Figures........................................................................vi
List of tables.........................................................................viii
Chapter 1    Introduction...........................................................1
1    Motivation.....................................................................1
2    Chapter Layout.................................................................2
Chapter 2    Theory Description and Literature Review...............................3
1    Brain-computer Interface System................................................3
2    Deep Brain Stimulation.........................................................4
3    Extracellular Microelectrode Neural Recording..................................5
3.1    In Vivo Microelectrode Array (MEA).............................................5
3.2    Local Field Potential and Action Potential.....................................5
3.3    Single-unit and Multi-unit Activity............................................6
4    Spike-sorting Algorithm........................................................6
4.1    Conventional Spike Sorting Strategy............................................6
4.2    Real-time and Offline Spike Sorting Algorithm..................................7
5    Open-source Spike Sorting Tool – Kilosort2.0..................................8
5.1    Pre-Processing.................................................................8
5.2    Spike Waveforms Model using Single-Value Decomposition (SVD)...................9
5.3    Electrical Data Model for Template Matching Framework..........................10
5.4    Learning and Inference with Template Matching Framework........................10
5.5    Speeding up spike sorting process..............................................11
6    Spike Sorting Hardware.........................................................11
6.1    Real-time Spike Sorting in a Wireless CL Optogenetics System...................11
6.2    Real-time Spike Sorting in a CL Neural-Interface System........................13
6.3    Real-time Spike-sorting Processor..............................................14
6.4    Discussion.....................................................................15
Chapter 3    Real-time Spike-sorting Algorithm......................................16
1    Pre-processing.................................................................16
2    Spike Detection................................................................16
3    Spike Alignment................................................................18
4    Feature Extraction.............................................................19
5    Clustering.....................................................................20
Chapter 4    Behavioral Simulation of Spike-sorting Algorithm.......................22
1    Single-channel Behavioral Simulation with Simulated Dataset....................22
1.1    Simulated Dataset..............................................................22
1.2    Single-channel Behavioral Simulation with MATLAB R2020b........................23
2    Multi-channel Behavioral Simulation with Neural Recording......................27
2.1    Neural Recording Data..........................................................27
2.2    Spike Sorting with KiloSort 2.0................................................28
2.3    32-channel Behavioral Simulation with MATLAB R2020b............................33
Chapter 5    Scalable 32-channel Spike Sorting Hardware.............................37
1    System Overview................................................................37
1.1    Extracellular Data from Analog Front-end.......................................37
1.2    Preprocessing Circuit..........................................................38
1.3    Spike Detection Circuit........................................................39
1.4    Spike Alignment Circuit........................................................39
1.5    Feature Extraction Circuit.....................................................40
1.6    Clustering Circuit.............................................................41
2    System Simulation Results......................................................43
3    Hardware Implementation on FPGA................................................43
3.1    Synthesis Results..............................................................43
4    Hardware Implementation on ASIC................................................44
4.1    Synthesis Results..............................................................44
5    Performance Analysis and System Scalability....................................45
6    Comparison with Previous Works.................................................46
Chapter 6    Conclusion and Future Work.............................................49
1.1    Conclusion.....................................................................49
1.2    Future work....................................................................49
References.............................................................................51
                                

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