研究生: |
郭廷鑫 Kuo, Ting-Hsin |
---|---|
論文名稱: |
三維式晶片堆疊封裝於直通矽晶穿孔結構與銅導線之可靠度分析 Reliability Analysis of Through Silicon Via (TSV) Structure and Copper Trace of 3D Chip Stacking Packaging |
指導教授: |
江國寧
Chiang, Kuo-Ning |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 動力機械工程學系 Department of Power Mechanical Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 123 |
中文關鍵詞: | 三維封裝技術 、直通矽晶穿孔 、熱循環分析 、可靠度 、Engelmaier關係式 、疲勞壽命 |
外文關鍵詞: | three-dimensional package technology, through silicon via, thermal cycle simulation, reliability analysis, Engelmaier fatigue model, fatigue life |
相關次數: | 點閱:4 下載:0 |
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隨著電子產品朝向輕、薄、短、小的目標與使用者的需求越來越高,電子封裝結構體內部各元件的尺寸也隨之縮減。為了大幅減少傳統二維式封裝技術所造成的缺點與限制,近年來,封裝產業界與研究單位均積極投入心力於三維式封裝技術的發展。在三維式封裝領域中,直通矽晶穿孔(Through Silicon Via, TSV)技術可有效提供晶片間在厚度方向之電訊連接,進而縮短其傳輸距離,成為該領域中較為突出且重視的一項技術。然而幾何尺寸的縮小造成結構中材料間的熱膨脹係數不匹配,導致在溫度負載下造成的散熱問題與熱應力集中等現象,仍是目前所面臨且需要克服的問題。
本研究主要目的在建立多層晶片堆疊之直通矽晶穿孔封裝體結構,以有限元素模型進行熱循環分析,並了解在承受溫度負載的情況下,各結構之力學行為之分析結果。透過文獻中對於該結構進行熱循環測試之實驗結果,找出其結構發生破壞的位置,同時驗證分析結果之正確性。為使有限元素模型在選擇材料與幾何尺寸的改變下,觀察其對於整體結構的影響,本研究透過參數化分析進行相關探討,並找出各參數間對於結構之影響程度。
透過文獻中銅導線分析與實驗相互驗證其可靠度之結果,本研究亦將以確立過網格密度之有限元素模型進行各項細部分析,找出其全應變值代入Engelmaier關係式以預估其疲勞壽命週期,最後以實驗所得之結果進行驗證。透過此方法將可有效預估的類似封裝結構內銅導線之可靠度壽命,作為日後相關研究中進行可靠度分析之參考依據。
參考文獻
[1] G. Q. Zhang, "Nanotechnologies and Electronics Packaging," Springer US, pp. 1-19, 2009.
[2] P. Pulici, G. Candela, G. Campardo, G. P. Vanalli, P. P. Stoppino, A. Losavio, T. Lessio, M. Dellutri, D. Guarnaccia, and F. Lo Iacono, "Interconnection Effects in Package on Package Design," Signal Propagation on Interconnects 2007, pp. 163-166, Ruta di Camogli, Italy, May 13-16, 2007.
[3] K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, and M. Bonkohara, "Ultra-High-Density Interconnection Technology of Three-Dimensional Packaging," Microelectronics Reliability, vol. 43, pp. 1267-1279, Aug. 2003.
[4] R. Landgraf, R. Rieske, A. N. Danilewsky, and K. J. Wolter, "Laser Drilled Through Silicon Vias: Crystal Defect Analysis by Synchrotron X-Ray Topography," Electronics System-Integration Technology Conference, pp. 1023-1028, Greenwich, London, UK, Sep. 1-4, 2008.
[5] S. Burkett, D. Temple, B. Stoner, C. Craigie, X. Qiao, and G. McGuire, "Processing Techniques for Vertical Interconnects," Semiconductor Device Research Symposium, pp. 403-406, Washington, DC, USA, Dec. 5-7, 2001.
[6] S. L. Burkett, X. Qiao, D. Temple, B. Stoner, and G. McGuire, "Advance Processing Techniques For Through-Wafer Interconnects," Journal of Vacuum Science Technology B, vol. 22, pp. 248-256, January 2004.
[7] S. Spiesshoefer and L. Schaper, "IC Stacking Technology using Fine Pitch, Nanoscale Through Silicon Vias," IEEE Electronic Components and Technology Conference, pp. 631-633, New Orleans, LA, USA, May 27-30, 2003.
[8] P. Dixit and J. Miao, "Fabrication of High Aspect Ratio 35 μm Pitch Interconnects for Next Generation 3-D Wafer Level Packaging by Through-wafer Copper Electroplating," Electronic Components and Technology Conference, pp. 388-393, San Diego, CA, USA, May 30-June 2, 2006.
[9] J. Jozwiak, R. G. Southwick, V. N. Johnson, W. B. Knowlton, and A. J. Moll, "Integrating Through-Wafer Interconnects With Active Devices and Circuits," IEEE Transactions on Advanced Packaging, vol. 31, No. 1, Feb. 2008.
[10] D. Henry, F. Jacquet, M. Neyret, X. Baillin, T. Enot, V. Lapras, C. Brunet-Manquat, J. Charbonnier, B. Aventurier, and N. Sillon, "Through Silicon Vias Technology for CMOS Image Sensors Packaging," IEEE Electronic Components and Technology Conference, pp. 556-562, Lake Buena Vista, Florida, USA, May 27-30 2008.
[11] S. Spiesshoefer, Z. Rahman, G. Vangara, S. Polamreddy, S. Burkett, and L. Schaper, "Process Integration for Through-Silicon Vias," Journal of vacuum science and technology, vol. 23, No.4, pp. 824-829, July 2005.
[12] M. Motoyoshi, "Through-Silicon Via (TSV)," Proceedings of the IEEE, vol. 97, pp. 43-48, Jan. 2009.
[13] H. H. Chang, Y. C. Shih, C. K. Hsu, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, "TSV Process Using Bottom-Up Cu Electroplating and its Reliability Test," Electronic System-Integration Technology Conference, pp. 645-650, Greenwich, London, UK, Sep. 1-4, 2008.
[14] H. H. Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, "3D Stacked Chip Technology Using Bottom-up Electroplated TSVs," Electronic Components and Technology Conference, pp. 1177-1184, San Diego, California, USA, May 26-29, 2009.
[15] C. S. Selvanayagam, J. H. Lau, Z. Xiaowu, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps," Electronic Components and Technology Conference, pp. 1073-1081, Florida, USA, May 27-30, 2008.
[16] N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Takahashi, "Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module," Electronic Components and Technology Conference, pp. 473-479, San Diego, California, USA, May 28-31, 2002.
[17] N. Tanaka, Y. Yamaji, T. Sato, and K. Takahashi, "Guidelines for Structural and Material-System Design of a Highly Reliable 3D Die-Stacked Module with Copper Through-Vias," Electronic Components and Technology Conference, pp. 597-602, New Orleans, Louisiana, USA, May 27-30, 2003.
[18] M. Umemoto, K. Tanida, Y. Neomoto, K. Hoshino, Y. Shirai, and K. Takahashi, "High-Performance Vertical Interconnection for High-Density 3D Chip Stacking Package," Electronic Components and Technology Conference, pp. 616-623, Las Vegas, USA, Jun. 1-4, 2003.
[19] K. Tanida, M. Umemoto, T. Morifuji, R. Kajiwara, T. Ando, Y. Tomita, N. Tanaka, and K. Takahashi, "Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology," Japanese Journal of Applied Physics, vol. 42, No. 10, pp. 6390-6395, Oct. 2003.
[20] T. Y. Kuo, S. M. Chang, Y. C. Shih, C. W. Chiang, C. K. Hsu, C. K. Lee, C. T. Lin, Y. H. Chen, and W. C. Lo, "Reliability Tests for a Three Dimensional Chip Stacking Structure with Through Silicon Via Connections and Low Cost," Electronic Components and Technology Conference, pp. 853-858, Florida, USA, May 27-30, 2008.
[21] M. C. Hsieh and C. K. Yu, "Thermo-Mechanical Simulations for 4-Layer Stacked IC Packages," 9th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2008, pp. 1-7, Freibug, Germany, May 2008.
[22] M. C. Hsieh, C. K. Yu, and W. Lee, "Effects of Geometry and Material Properties for Stacked IC Package with Spacer Structure," 10th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2009, Netherlands, April 27-29, 2009.
[23] Y. C. Shih, T. Y. Kuo, Y. P. Hung, J. Y. Chang, C. Y. Cheng, K. C. Chen, C. K. Lee, C. K. Hsu, J. H. Huang, Z. C. Hsiao, C. T. Ko, and Y. H. Chen, "Manufacturing and Stacking of Ultra-Thin Film Packages," Electronic Components and Technology Conference, pp. 1440-1446, San Diego, California, USA, May 26-29, 2009.
[24] M. C. Yew, C. J. Wu, C. S. Huang, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, Florida, USA, May 28-31, 2008.
[25] M. C. Yew, C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and K. N. Chiang, "Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging," IEEE Transactions on Advanced Packaging, vol. 32, No.2, pp. 390-398, May 2009.
[26] M. C. Yew, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, "Reliability analysis of a novel fan-out type WLP," Soldering & Surface Mount Technology, vol. 21, pp. 30-38, 2009.
[27] M. C. Yew, C. Y. Chou, and K. N. Chiang, "Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis," Microelectronics Reliability, vol. 47, pp. 1658-1662, September-November 2007.
[28] L. F. Coffin and N. Y. Schenectady, "A Study of the Effects of Cyclic Thermal Stress on a Ductile Material," Transactions of ASME, vol. 76, pp. 931-950, 1954.
[29] S. S. Manson, "Thermal Stress and Low Cyclic Fatigue," McGraw Hill, pp. 125-192, New York, 1966.
[30] W. Engelmaier, "Results of the IPC Copper Foil Ductility Round-Robin Study," Testing of Metallic and Inorganic Coatings, pp. 66-95, ASTM STP947, Philadepphia, USA, 1987.
[31] W. Engelmaier, "Flexural Fatigue and Ductility, Foil," IPC-TM-650, Institude for Interconnecting and Packaging Electronic Circuits, Lincolnwood, USA, 1980.
[32] W. Engelmaier, "A New Ductility and Flexural Fatigue Test Method for Copper Foil and Flexible Printed Wiring," Proceedings IPC, IPC-TP-204, Washington, USA, 1978.
[33] W. Engelmaier and A. Wagner, "Fatigue Behaviour and Ductility Determination for Roller Annealed Copper Foil and Flex Circuits on Kapton," Circuit World, vol. 14, No. 2, pp. 30-38, 1988.
[34] R. R. Tummala, P. Markondeya Raj, A. Aggarwal, G. Mehrotra, K. Sau Wee, S. Bansal, T. Tan Teck, C. K. Ong, J. Chew, K. Vaidyanathan, and V. Srinivasa Rao, "Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications," Electronic Components and Technology Conference, pp. 102-111, 0-0 0 San Diego, CA, USA, May 30-June 2, 2006.
[35] A. S. Prabhu, D. B. Barker, and M. G. Pecht, "A Thermo-Mechanical Fatigue Analysis of High Density Interconnect Vias," ASME Advances in ElectronicPackaging, vol. 10-1, pp. 187-216, 1995.
[36] B. Z. Hong, "Thermal Fatigue Analysis of a CBGA Package with Lead free Solder Fillets," InterSociety Conference on Thermal Phenomena, pp. 205-211, Seattle, Washington, USA, May 27-30, 1998.
[37] H. L. Pang, T. H. Low, and B. S. Xiong, "Lead-Free 95.SSn-3.8Ag-0.7Cu Solder Joint Reliability Analysis For Micro-BGA Assembly," Inter Society Conference on thermal phenomena, pp. 131-136, Las Vegas, USA, June 1-4, 2004.
[38] C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder Joint and Trace Line Failure Simulation and Experimental Validation of Fan-Out Type Wafer Level Packaging Subjected to Drop Impact," ESREF2008, Maastricht, Netherland, Sep. 30 - Oct. 3, 2008
[39] C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang, and K. N. Chiang, "Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test," EuroSimE2008, Freiburg im Breisgau, Germany, April 20-23, 2008.
[40] C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via," Materials for Advanced Metallization Conference, MAM 2009, Grenoble, France, Mar. 8-11, 2009.
[41] L. J. Segerlind, "Applied Finite Element Analysis," Wiley, 2nd Edition, New York, USA, 1984.
[42] 江國寧, "微電子矽統封裝基礎理論與應用技術," 滄海書局, 2006.
[43] J. Lau, C. P. Wong, J. L. Prince, and W. Nakayama, "Electronic Packaging Design, Materials, Process, and Reliability," McGraw Hill, Washington, D. C., USA, 1998.
[44] W. F. Chen and D. J. Han, "Plasticity for Structural Engineers," Cau Lih, pp. 239-249, Taipei,Taiwan, 1995.
[45] R. D. Cook, D. S. Malkus, and M. E. Plesha, "Concepts and Applications of Finite Element Analysis " Wiley, 4th Edition, pp. 504-505, New York, USA, 1989.
[46] J. E. Shigley, C. R. Mischke, and R. G. Budynas, "Essentials of Mechanical Engeering Design," McGraw Hill, New York, USA, 2004.
[47] J. M. Gere, "Mechanics of Materials," Springer-Verlag, 7th Edition, 1994.
[48] J. A. Collins, "Failure of Materials in Mechanical Design," John Wiley & Sons, 2nd Edition, 1981.
[49] M. J. Pfeifer, "Solder Bump Size and Shape Modeling and Experimental Validation," IEEE Transactions on Components, Packaging and Manufacturing Technology - Part B, vol. 20, No.4, pp. 452-457, 1997.
[50] S. M. Heinrich, M. Schaefer, S. A. Schroeder, and P. S. Lee, "Prediction of Solder joint Geometries in Array-Type Interconnects," ASME J. Electron. Packag., vol. 118, pp. 114-121, 1996.
[51] K. N. Chiang and W. L. Chen, "Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array," ASME Transactions on Journal of Electronic Packaging, vol. 120, No.2, pp. 175-178, 1998.
[52] K. A. Brakke, "The Surface Evolver," Experimental Mathematics, vol. 1, No.2, pp. 141-165, 1992.
[53] K. A. Brakke, "Surface Involver Manual," version 2.01 Minneapolis, MN:The Geometry Center, 1996.
[54] K. A. Brakke, "The Surface Evolver and the Stability of Liquid Surface," Philosophical Transactions: Mathematical Physical and Engineering Sciences, vol. 354, pp. 2143-2157, 1996.
[55] L. Li and B. H. Yeung, "Wafer Level and Flip Chip Design Through Solder Prediction Models and Validation," IEEE Transactions on Components and Packaging Technologies, vol. 24, No.4, pp. 650-654, 2001.
[56] B. H. Yeung and T. Y. T. Lee, "Evaluation and Optimization of Package Processing, Design, and Reliability through Solder Joint Profile Prediction," IEEE Electronic Components and Technology Conference, pp. 925-930, Orlando, Florida, USA, May 29-June, 1 2001.
[57] K. N. Chiang and C. Y. Yuan, "An Overview of Solder Bump Shape Prediction Algorithm with Validations," IEEE Transactions on Components and Packaging Technologies, vol. 24, No.2, pp. 158-162, 2001.
[58] S. B. Lee, I. Kim, and T. S. Park, "Fatigue and Fracture Assessment for Reliability in Electronics Packaging " International Journal of Fracture, vol. 150, No. 1-2, pp. 91-104, July 2008.
[59] S. H. Dai and M. O. Wang, "Reliability Analysis in Engineering Applications," John Wiley & Sons, pp. 337-397, New York, USA, 1992.
[60] N. R. Mann, R. E. Schafer, and N. D. Singpurwalla, "Methods for Statistical Analysis of Reliability and Life Data," John Wiley & Sons, pp. 184-258, New York, USA, 1974.
[61] J. H. Lau and Y. H. Pao, "Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies," McGraw Hill, pp. 29-32, New York, USA, 1997.
[62] R. Darveaux, K. Banerji, A. Mawer, and G. Dody, "Reliability of Plastic Ball Grid Array Assembly," McGraw Hill, pp. 379-442, New York, USA, 1995.
[63] R. Darveaux, "Effects of Simulation Methodology on Solder Joint Crack Growth Correlation," Proc. of the 50th Electronic Components and Technology Conference, pp. 1048-1058, Los Vegas, USA, 2000.
[64] V. Gektin, A. Bar-Cohen, and J. Ames, "Coffin-Manson Fatigue Model of Underfilled Flip-Chips," IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 20, No.3, pp. 317-326, Sep. 1997.
[65] J. H. Lau, "Experimental and Analytical Studies of 28-pin Thin Small Outline Package (TSOP)," ASME Journal of Electronic Package, vol. 114, pp. 169-176, 1992.
[66] R. Satoh, K. Arakawa, M. Harada, and K. Matsui, "Thermal Fatigue Life of Pb-Sn Alloy Interconnections," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14, No.1, pp. 224-232, Mar. 1991.
[67] M. Sakurai, H. Shibuya, and J. Utsunomiya, "FEM Analysis of Flip-Chip Type BGA," Proc. of IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 131-136, Berlin, Germany, 1998.
[68] H. D. Solomon, "Fatigue of 60/40 Solder," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 9, No.4, pp. 423-432, Dec. 1986.
[69] R. V. Pucha, G. Ramakrishna, and S. K. Sitaraman, "Modeling Spatial Strain Gradient Effects in Thermo-Mechanical Fatigue of Copper Microstructures," International Journal of Fatigue, vol. 26, No.9, pp. 947-957, 2004.
[70] R. Iannuzzelli, "Predicting Plated-Through-Hole Reliability in High Temperature Manufacturing Processes," Electronic Components and Technology Conference, pp. 410-421, Atlanta, USA, May 11-16, 1991.
[71] M. C. Hsieh and W. Lee, "FEA Modeling and DOE Analysis for Design Optimization of 3D-WLP," Electronic Systemintegration Technology Conference, pp. 707-712, Greenwich, UK, Sep. 1-4, 2008.
[72] JEDEC Solid State Technology Association, "Temperature Cycling," JEDS22-A104-B, EIA/JEDEC, USA, 2000.
[73] K. O. Lee, J. Yu, T. S. Park, and S. B. Lee, "Low-Cycle Fatigue Characteristics of Sn-Based Solder Joints," Journal of Electronic Materials, vol. 33, No.4, pp. 249-257, 2004.