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研究生: 郭廷鑫
Kuo, Ting-Hsin
論文名稱: 三維式晶片堆疊封裝於直通矽晶穿孔結構與銅導線之可靠度分析
Reliability Analysis of Through Silicon Via (TSV) Structure and Copper Trace of 3D Chip Stacking Packaging
指導教授: 江國寧
Chiang, Kuo-Ning
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 動力機械工程學系
Department of Power Mechanical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 123
中文關鍵詞: 三維封裝技術直通矽晶穿孔熱循環分析可靠度Engelmaier關係式疲勞壽命
外文關鍵詞: three-dimensional package technology, through silicon via, thermal cycle simulation, reliability analysis, Engelmaier fatigue model, fatigue life
相關次數: 點閱:4下載:0
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  • 隨著電子產品朝向輕、薄、短、小的目標與使用者的需求越來越高,電子封裝結構體內部各元件的尺寸也隨之縮減。為了大幅減少傳統二維式封裝技術所造成的缺點與限制,近年來,封裝產業界與研究單位均積極投入心力於三維式封裝技術的發展。在三維式封裝領域中,直通矽晶穿孔(Through Silicon Via, TSV)技術可有效提供晶片間在厚度方向之電訊連接,進而縮短其傳輸距離,成為該領域中較為突出且重視的一項技術。然而幾何尺寸的縮小造成結構中材料間的熱膨脹係數不匹配,導致在溫度負載下造成的散熱問題與熱應力集中等現象,仍是目前所面臨且需要克服的問題。
      本研究主要目的在建立多層晶片堆疊之直通矽晶穿孔封裝體結構,以有限元素模型進行熱循環分析,並了解在承受溫度負載的情況下,各結構之力學行為之分析結果。透過文獻中對於該結構進行熱循環測試之實驗結果,找出其結構發生破壞的位置,同時驗證分析結果之正確性。為使有限元素模型在選擇材料與幾何尺寸的改變下,觀察其對於整體結構的影響,本研究透過參數化分析進行相關探討,並找出各參數間對於結構之影響程度。
      透過文獻中銅導線分析與實驗相互驗證其可靠度之結果,本研究亦將以確立過網格密度之有限元素模型進行各項細部分析,找出其全應變值代入Engelmaier關係式以預估其疲勞壽命週期,最後以實驗所得之結果進行驗證。透過此方法將可有效預估的類似封裝結構內銅導線之可靠度壽命,作為日後相關研究中進行可靠度分析之參考依據。


    目錄 中文摘要…………………………………………………...……………..i 英文摘要…………………………………………………...…………....iii 目錄………………………………………………………………………v 表目錄……………………………………………………………….…viii 圖目錄………………………………………………………………....…x 第一章  緒論………………….………………………………..….……1 1-1 電子封裝簡介………………………………….………….…...1 1-2 三維式封裝體結構……………………………………….……3 1-3 研究動機………………………………………………….…....9 1-4 文獻回顧………………………………………………….…..10 1-5 研究目標…………………………………………………...…25 第二章 基礎理論………………………..……..…………………........27 2-1 線彈性固體力學有限元素理論分析…………………….…..27 2-2 材料非線性有限元素理論分析……………….……….…….32 2-3 數值分析與收斂準則……………………….…………..……34 2-4 破壞準則………………………………………….…….….…36 2-4-1 最大正向應力理論…………………….…………..…37 2-4-2 Tresca準則…………………………….……………....38 2-4-3 von Mises準則………………………….………….….39 2-5 錫球外型預估…………………………………….…….….…40 2-6 可靠度分析…………………………………….……………..42 2-6-1 韋伯分布函數………………………….………...…...43 2-6-2 錫球可靠度分析……………………….…………......45 2-6-3 導線可靠度分析……………………….…………......47 第三章 研究方法……………….……………..……….…………........52 3-1 結構體之幾何尺寸與有限元素模型的建立…………….…..53 3-2 封裝體結構之材料性質……………………….……….…….55 3-3 封裝體結構之邊界條件與負載設定……….…………..……57 3-4 封裝體結構之參數化分析……………………….…….….…63 3-5 封裝體結構之可靠度分析……………………….…….….…65 第四章 有限元素分析結果…….……………..……….…………........66 4-1 熱循環測試下的晶片翹曲行為………………………….…..66 4-2 熱循環測試下的應力行為…………………….……….…….71 4-2-1 晶片的應力行為……………………….…………..…71 4-2-2 導孔的應力行為…..………………….……………....73 4-2-3 凸塊的應力行為……………………….………….….75 4-2-4 導線的應力行為……………………….………….….78 4-3 熱循環測試下的應變行為…………………….……….…….81 4-3-1 導線的應變行為……………………….…………..…81 4-3-2 網格密度變化的應變趨勢..………….……………....82 4-4 基板材料對於封裝體結構的影響……………….…….…….84 4-4-1 不同基板材料之翹曲量分析………….…………..…85 4-4-2不同基板材料之應力分析..………………...………....87 4-5 封裝體結構之參數化分析結果……….…………..…………89 4-5-1 底膠效應之參數化分析……………….…………..…90 4-5-2 ABF絕緣層厚度之參數化分析.…………...………....92 4-5-3 銅導孔半徑之參數化分析.…………...…...………....95 4-5-4 銅導線寬度之參數化分析.…………...…...………....97 第五章 可靠度分析與驗證…….……………..…..….…………........100 5-1 網格密度之設定…………………..………….…………....101 5-2 銅導線之疲勞壽命分析…………..………….……………102 5-3 含PCB封裝體結構之可靠度分析……………..…………106 第六章 結論…….……………..……….…………..............................112 參考文獻………………………………………………………………116 表目錄 表1-1、導孔製程比較…………………………………...…………….....7 表1-2、不同凸塊高度下結構的熱循環測試之可靠度………………..14 表1-3、不同合金比例的錫球之Coffin-Manson相關係數……….……22 表1-4、不同材料之Coffin-Manson可靠度關係式……………….……23 表3-1、封裝體結構幾何尺寸……………………………...…………...54 表3-2、電鍍銅材料應力-應變關係 (27℃) …………...…………..…..56 表3-3、電鍍銅材料應力-應變關係 (260℃) …………...……………..56 表3-4、不同溫度下電鍍銅材料性質…………...……………………...56 表3-5、材料性質表………...……………………………………...…....57 表3-6、溫度循環測試條件………...…………………………………...62 表4-1、不同堆疊層數之底層晶片翹曲量……………………………..70 表4-2、不同晶片堆疊層數之晶片最大第一主軸應力值……………..72 表4-3、不同晶片堆疊層數之導孔最大von Mises應力值…………….75 表4-4、兩層晶片堆疊層數之角落凸塊von Mises應力值…………….77 表4-5、不同晶片堆疊層數之底層凸塊最大von Mises應力值….…....78 表4-6、不同晶片堆疊層數之底層角落導線最大von Mises應力值….80 表4-7、封裝體材料性質表………………………………………........85 表4-8、不同基板材料之晶片翹曲量分析……………………………..87 表4-9、底膠效應參數化分析下之應力-應變行為…………………….91 表4-10、ABF絕緣層厚度參數化分析下之應力-應變行為…………...94 表4-11、銅導孔半徑參數化分析下之應力-應變行為………………...96 表4-12、導線寬度參數化分析下之應力-應變行為………………….98 表5-1、各個循環下在銅導線位置之von Mises全應變數值…...……104 表5-2、有限元素模型分析與實驗之驗證…………………….……...106 表5-3、封裝體結構幾何尺寸…………………….…………………..109 表5-4、兩材料結構之應變與疲勞壽命之比較……………………….111 圖目錄 圖1-1、摩爾定律(Moore’s Law)與新摩爾定律(More than Moore)….…4 圖1-2、系統式封裝示意圖………………………………………………5 圖1-3、封裝體堆疊(PoP)結構示意圖…………………………………...6 圖1-4、晶片堆疊(CoC)結構示意圖………………………………..……6 圖1-5、Bottom-Up製程之直通矽晶穿孔結構………………………..…8 圖1-6、直通矽晶穿孔封裝體結構…………………………………..…10 圖1-7、全域與局域之直通矽晶穿孔封裝體結構…………………..…11 圖1-8、直通矽晶穿孔封裝體結構示意圖……………..………………12 圖1-9、三維式封裝體結構之有限元素模型…………..………………13 圖1-10、不同底膠比例下結構的等效塑性應變趨勢…………..……..13 圖1-11、銅凸塊等效塑性應變分布……………………………..……..14 圖1-12、三維式直通矽晶穿孔結構……………………………..……..16 圖1-13、三維式晶片堆疊結構示意圖…………………………..……..16 圖1-14、熱循環測試之韋伯分布函數………..………………………..17 圖1-15、熱循環測試下SEM剖面觀測圖……..……………………….17 圖1-16、三維式封裝體結構示意圖……..……………………………..18 圖1-17、熱循環模擬下各結構之應力分布情形..……………………18 圖1-18、四分之一幾何對稱模型..……………………………………..19 圖1-19、銅導線與導孔、墊片間之結構分布情形..……………………19 圖1-20、嵌板式電子封裝結構實際結構..……………………………..21 圖1-21、封裝結構示圖..………………………………………………22 圖1-22、封裝結構破壞區域比較..…………………………………..…22 圖1-23、封裝結構在熱循環測試下的韋伯分布函數..……………......23 圖1-24、不同材料之塑性應變-疲勞壽命關係圖..………………….....24 圖2-1、等向硬化法則..…………………………………………………33 圖2-2、動態硬化法則..…………………………………………………34 圖2-3、全牛頓-拉夫森法之外力-位移關係圖..……………………..…36 圖2-4、彎曲測試之最大應變分布示意圖..……………………………49 圖2-5、電鍍銅薄膜之應變-疲勞壽命關係..………………………...…50 圖3-1、直通矽晶穿孔封裝結構..…………………………………….53 圖3-2、直通矽晶穿孔封裝結構示意圖……………………………..…54 圖3-3、電鍍銅材料應力-應變曲線…………………………………….57 圖3-4、工研院直通矽晶穿孔封裝結構上視圖……………………..…59 圖3-5、封裝體結構四分之一對稱模型……………………………..…59 圖3-6、封裝體結構之邊界條件設定………………………………..…60 圖3-7、電訊傳輸結構之有限元素模型分布圖……………………..…60 圖3-8、JEDEC之加速熱循環負載之溫度變化……………………..…62 圖3-9、模擬加速熱循環負載之溫度變化…………………………..…63 圖3-10、不同晶片堆疊層數之有限元素模型……………………….64 圖4-1、不同晶片堆疊層數之模型翹曲行為@-55℃……………….....67 圖4-2、不同晶片堆疊層數之模型翹曲行為@125℃……………….....67 圖4-3、兩層晶片堆疊模型之翹曲行為@-55℃…………………….....69 圖4-4、兩層晶片堆疊模型之翹曲行為@125℃……………………...69 圖4-5、不同晶片堆疊層數之底層晶片翹曲量……………………......70 圖4-6、兩層晶片堆疊模型之晶片第一主軸應力分布情形…………..72 圖4-7、不同晶片堆疊層數之晶片第一主軸應力變化………………..73 圖4-8、兩層晶片堆疊模型之導孔von Mises應力分布情形………….74 圖4-9、不同晶片堆疊層數之導孔von Mises應力變化……………….75 圖4-10、兩層晶片堆疊層數模型之角落凸塊模型…………………....76 圖4-11、底層凸塊與基板之四分之一對稱模型……………………..77 圖4-12、底層凸塊之von Mises應力分布情形………………………...77 圖4-13、不同晶片堆疊層數之底層凸塊von Mises應力變化…….......78 圖4-14、底層之導線有限元素模型……………………………………79 圖4-15、底層角落導線之von Mises應力分布情形…………………...80 圖4-16、不同晶片堆疊層數之底層導線von Mises應力變化………...80 圖4-17、底層角落導線之等效塑性應變分布情形…………………....82 圖4-18、結構破壞位置比較…………………………………………....82 圖4-19、不同網格密度之導線模型…………………………………....83 圖4-20、不同網格密度之導線等效塑性應變趨勢…………………....84 圖4-21、BT基板之有限元素模型……………………………………...85 圖4-22、兩層晶片堆疊模型之翹曲量分布@125℃……………….......86 圖4-23、不同基板材料之下層晶片翹曲量分布@125℃……………...87 圖4-24、底層導線之von Mises應力分布圖…………………………...88 圖4-25、頂層導線之von Mises應力分布圖…………………………...89 圖4-26、填有底膠之封裝體結構示意圖……………………………....91 圖4-27、ABF絕緣層製程下之厚度差異比較………………………....92 圖4-28、ABF厚度參數化之有限元素模型…………………………....93 圖4-29、ABF絕緣層厚度參數化分析下之應力趨勢圖………………94 圖4-30、導孔半徑參數化之有限元素模型…………………………....95 圖4-31、導孔半徑參數化分析下之應力趨勢圖……………………....97 圖4-32、銅導線模型之幾何尺寸……………………………………....99 圖5-1、嵌板式電子封裝結構之有限元素模型………………………101 圖5-2、細部銅導線之有限元素模型………………………………....103 圖5-3、銅導線之von Mises全應變數值分佈圖……………………...104 圖5-4、銅導線之von Mises全應變數值趨勢………………………...105 圖5-5、含PCB之封裝體結構側視圖………………………………....107 圖5-6、含PCB之封裝體結構四分之一對稱示意圖…………………107 圖5-7、含PCB之封裝體有限元素模型……………………………....108 圖5-8、底層PCB板與錫球之有限元素模型…………………………108 圖5-9、溫度相關之非線性材料性質(95.5Sn-3.8Ag-0.7Cu) …...……109

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