摘 要

雖然可以藉由高濃度的摻雜析離層這項技術，有效的調變蕭特基能障的分布來改善蕭特基金氧半元件特性。但是具備摻雜析離層的蕭特基金氧半元件相較於傳統金氧半電晶體，在短通道行為的表現上，會因摻雜析離層造成的延伸，使的元件的特性更為惡化。並且也可以觀察到，即便是有這層高濃度摻雜析離層，其雙向導通行為會隨短通道之微縮而顯著退化。如同傳統的金氧半電晶體，為了能有效去控制短通道行為，利用經過最佳化的側邊環狀佈植。可惜的是當使用了側邊環狀佈植，具備摻雜析離層的蕭特基金氧半元件呈現出嚴重且無法接受的雙向導通電洞流以及價帶至傳導帶間穿隧電流。並且當濃度提高時，情況會更為嚴重。而在具備摻雜析離層的蕭特基金氧半元件利用絕緣層覆矽晶基板這方面，也會經由埋入氧化層所產生的通道位能勢缺陷，導致額外熱發射電子流的形成，進而限制了元件的轉換特性。
因此其元件的發展仍存在許多的挑戰，為了因應具備摻雜析離層的蕭特基金氧半元件在未來繼續微縮的可能性，本篇論文提出一種具絕緣介電氧化層產生超淺延伸接面的蕭特基元件架構，解決上述所提到的問題並提高原有的元件特性。而所有研究結果都是藉由二維的模擬軟體來完成。在高濃度的摻雜析離層與環狀佈植之間，經由利用絕緣介電氧化層來隔絕後，橫向穿透電場明顯的降低並使得價帶至傳導帶間穿隧電流同時下降。除此之外，電洞蕭特基能障窄化現象的減輕，也讓雙極性電洞流降至一個對元件特性影響可忽略的程度。因此，就可以利用一個最佳化的環狀佈植來有效的控制短通道行為，而不會伴隨其它漏電流的機制。另外在此架構下，可以完全性的消除元件通道經由埋入氧化層產生電壓偶合而導致位能勢下降的現象。所以在保有高濃度的摻雜析離層其優點的同時，也能利用環狀佈植來有效的控制短通道行為，這樣顯著的良好特性，可使得摻雜析離式蕭特基金氧半元件在未來的發展上更有潛力。

ABSTRACT

Although the dopant segregation (DS) technique can efficiently modify a Schottky barrier to improve SBMOS, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. As in traditional MOSFETs, lateral halo profile must be used together with minimization of vertical dimensions to control efficiency the short-channel behaviors of DS-SBMOS. Unfortunately, the ambipolar hole current and the band-to-band tunneling leakage are significantly aggravated due to the parasitic N+ extension/P+ halo junction. In addition, it can be found that the degradation in subthreshold current is observed for the use of silicon-on-insulator (SOI) structure. The potential of channel region decreases due to the stronger gate control, and the potential weakness results in significant subsurface thermal emission electron current that limits the switching characteristics of SOI DS-SBMOS.
An Insulated Dielectric Oxide (IDO) structure is presented for the DS-SBMOS devices to suppress the unwanted on- and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, the lateral electrical field can be significantly lowered leads to band-to-band leakage currents are minimized. It also relieves the narrowing of the hole Schottky barrier in the drain region to yield a neglected ambipolar hole current. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Besides, the IDO structure also eliminates the potential weakness because the channel potential is not coupling via the buried oxide layer. The design of IDO DS-SBMOS combines both the merits of dopant segregation technique and ideal halo profile to serve as an attractive candidate for next-generation CMOS devices.

REFERENCE

[1] The International Technology Roadmap for Semiconductors 2009 (ITRS).
[2] M. M. Pelella and J. G. Fossum, “On the performance advantage of PD/SOI CMOS with floating bodies,” IEEE Trans. Electron Devices, vol. 49, pp. 96-104, Jan. 2002.
[3] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET: a self-aligned double-gate MOSFET scalable to 20 nm, ” IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, Dec. 2000.
[4] D. A. Muller, T. Sorsch, S. Moccio, F. H. Baumann, K. Evans-Lutterodt, and G. Timp, “Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures,” in Nature, 1999, pp. 758-761.
[5] M. Bohr, “Intel’s 90 nm logic technology using strained silicon transistors,” in IEDM Tech. Dig., 2003.
[6] S. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Schottky barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode,” IEEE Electron Device Lett., vol. 25, pp. 268-270, May. 2004.
[7] J. Kedzierski, P. Xuan, E. Anderson, J. Bokor, T. J. King, and C. Hu, “Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime, ” in IEDM Tech. Dig., 2000, pp. 57-60.
[8] G. Larrieu and E. Dubois, “Integration of PtSi-based Schottky barrier p-MOSFETs with a midgap tungsten gate,” IEEE Trans. Electron Devices, vol. 52, pp. 2720-2726, Dec. 2005.
[9] C. Wang, J. P. Snyder, and J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors, ” Appl. Phys. Lett., vol. 74, pp. 1174-1176, Feb. 1999.
[10] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schotky barrier contact for source and drain,” in Proceedings of the IEEE, vol. 56, pp. 1400-1402, 1968.
[11] D. Kahng and M. M. Atalla, “Silicon-Silicon Dioxide field induced devices,” in Device Research Conf., 1960.
[12] J. P. Snyder, C. R. Helms, and Y. Nishi, “Experimental investigation of a PtSi source and drain field emission transistor,” Appl. Phys. Lett., vol. 67, pp. 1420-1422, Sep. 1995.
[13] L. E. Calvet, H. Luebben, M. A. Reed, C. Wang, J. P. Snyder, and J. R. Tucker, “Suppression of leakage current in Schottky barrier metal-oxide-semiconductor field-effect transistors, ” Jpn. J. Appl. Phys., vol. 91, pp. 757-759, Jan. 2002.
[14] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of short-channel Schottky source/drain MOSFET on Silicon-on-Insulator substrate demonstration of sub-50-nm n-type devices with metal gate,” Jpn. J. Appl. Phys., part 1, vol. 38, pp. 6226-6231, Nov. 1999.
[15] J. Knoch and J. Appenzeller, “Impact of the channel thickness on the performance of Schottky barrier metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 81, pp. 3082-3084, Jul. 2002.
[16] M. Nishisaka, S. Matsumoto, and T. Asano, “Schottky source/drain SOI MOSFET with shallow doped extension,” Jpn. J. Appl. Phys., part 1, vol. 42, pp. 2009-2013, Dec. 2003.
[17] M. Jang, Y. Kim, M.Jeon, C. Choi, B. Park, and S. Lee, “Ambipolar carrier injection characteristics of Erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors,” Jpn. J. Appl. Phys., vol. 45, pp. 730-732, Nov. 2006.
[18] D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, “A new route to zero-barrier metal source/drain MOSFETs,” IEEE Trans. Nanotechnol., vol. 3, pp. 98-104, 2004.
[19] J. Chen S. Zhu, M. F. Li, S. J. Lee, J. Singh, C. X. Zhu, A Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier source/drain MOSFET using Ytterbium silicide, ” IEEE Electron Device Lett., vol. 25, pp. 565-567, Aug. 2004.
[20] A. Yagishita, T.-J. King, and J. Bokor, “Schottky barrier height reduction and drive current improvement in metal source/drain MOSFET with strained-Si channel,” Jpn. J. Appl. Phys., vol. 43, pp. 1713-1716, Apr. 2004.
[21] D. E. Grupp, D. Connelly, C. Faulkner, and P. A. Clifton, “A new junction technology for low-resistance contacts and Schottky barrier MOSFETs,” In 2005 Intern. Workshop on Junction Technology, 2005.
[22] D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, “A new route to zero-barrier metal source/drain MOSFETs,” IEEE Trans. Nanotechnol., vol. 3, pp. 98-104, 2005.
[23] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for highperformance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,” In Digest of 2004 Symposium on VLSI Technology, 2004.
[24] Z. Zhang, Z. Qiu, R. Liu, M. Ostling, and S. Zhang, “Schottky-barrier height tuning by means of Ion Implantation into preformed silicide films followed by drive-in anneal,” IEEE Electron Device Lett., vol. 28, pp. 565-568, July. 2007.
[25] T. Yamauchi, Y. Nishi, Y. Tsuchiya, A. Kinoshita, J. Koga and K. Kato, “Novel doping technology for a 1nm NiSi/Si junction with dipoles comforting Schottky (DCS) barrier,” in IEDM Tech. Dig., 2007, pp. 963-966.
[26] J. Knoch, M. Zhang, and J. Appenzeller, “On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 1669-1674, Jul. 2006.
[27] Synopsys MEDICI User‘s Manual, CA, 2006.
[28] Synopsys TSUPREM-4 User’s Manual, Synopsys Inc., Mountain View, CA, 2006.
[29] W. Schottky, Semiconductor theory of the barrier film, Naturwissenschaften, 1938.
[30] R. S. Muller and T. I. Kamins, Device electronics for integrated circuits, Jon Wileys & Sons, 1988.
[31] J. Bardeen, Surface states and rectification at a metal semiconductor contact, Phys. Rev., 1947, pp. 717-727.
[32] E. H. Rhoderick and R. H. Wiliams, Metal-semiconductor contacts, Clarendon Press, 1988.
[33] A. Tanabe, K. Konuma, N. Teranishi, S. Tohyama, and K. Masubuchi, “Influence of Fermi-level pinning on barrier height inhomogeneity in PtSi/p-Si Schottky contacts,” Jpn. J. Appl. Phys., vol. 69, pp. 850-853, Jan. 1991.
[34] S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Electron Devices, vol. 52, pp. 1859-1867, Aug. 2005.
[35] J. M. Andrews and M. P. Lepselter, “Reverse current-voltage characteristics of metal-silicide Schottky diodes,” Solid-State Electronics, vol. 13, pp. 1011-1023, 1970.
[36] N. Agrawal, J. Chen, Z. Hui, Y.-C. Yeo, S. Lee, D. S. H. Chan, M.-F. Li, G.. S. Samudra, “Interface barrier abruptness and work function requirements for scaling Schottky source-drain MOS transistors,” in Proc. SISPAD 2006, pp. 139-142.
[37] H. A. Bethe, Theory of the boundary layer of crystal rectifiers, MIT Radiation Lab. Rep., 1942.
[38] C. R. Crowell and S. M. Sze, “Current transport in Metal-Semiconductor barriers,” Solid-State Electronics, vol. 9, pp. 1035-1048, 1966.
[39] C. S. Kang, H. J. Cho, K. Onishi, R. Choi, R. Nieh, S. Goplan, S. Krishnan, and J. C. Lee, “Improved thermal stability and device performance of ultrathin gate dielectrics MOSFETs by using hafnium oxynitride, ” in Symp. VLSI Tech. Dig., 2000, pp. 146-157.
[40] M. Jang, J. Oh, S. Maeng, W.Cho, K. Kang, and K. Park, “Characteristics of erbium silicided n-type Schottky barrier tunnel transistors,” Appl. Phys. Lett., vol. 83, pp. 2611-2613, Aug. 2003.
[41] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate, ” Jpn. J. Appl. Phys., vol. 38, pp. 6226-6231, Aug. 1999.
[42] M. C. Ozturck, “Channel, source/drain and contact engineering for 45 nm, ” Technical report, IEDM2004 Short Course.
[43] J. Yuan, P. M. Zeitzoff, and J. C. S. Woo, “Source/drain parasitic resistance role and electrical couple effect in sub 50 nm MOSFET design, ” in ESSDERC Tech. Dig., 2002, pp. 503-506.
[44] L. E. Calvet, H. Luebben, M. A. Reed, C. Wang, J. P. Snyder, and J. R. Tucker, “Subthreshold and scaling of PtSi Schottky barrier MOSFETs, ” Super;attics and Microstructures, 2000, pp. 501-506.
[45] M. Nishisaka, S. Matsumotom, and T. Asano, “Schottky source/drain SOI MOSFET with shallow doped extension,” Jpn. J. Appl. Phys., vol. 42, pp. 2009-2013, Dec. 2003.
[46] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for high performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant-segregation technique,” in Symp. VLSI Tech. Dig., 2004, pp. 168-169.
[47] C. H. Shih and S. P. Yeh, “Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs,” Semicond. Sci. Technol., vol. 23, Nov 2008.

[48] Z. Zhang, Z. Qiu, P.-E. Hellstrom, G. Malm, J. Olsson, J. Lu, M. Ostling, and S.-L. Zhang, “SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation,” IEEE Electron Device Lett., vol. 29, pp. 125-127, Jan. 2008.
[49] Y. Taur, C. H. Wann, and D. J. Frank, “25nm CMOS design considerations, ” in IEDM Tech. Dig., 1998, pp. 789-792.
[50] B. Yu, H. Wang, O. Milic, Q. Xiang, W. Wang, J. X. An, and M. R. Lin, “50nm gate-length CMOS transistor with super-halo: design, process, and reliability, ” in IEDM Tech. Dig., 1999, pp. 653-656.