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研究生: 曹哲豪
Tsao, Che-Hao
論文名稱: Study of Staged Trap Generation and Spatial Trap Distribution in High-K Gated MOSFETs by Charge Pumping
應用電荷汲引技術於高介電係數閘極電晶體階段缺陷增生與空間之量測研究
指導教授: 張廖貴術
Chang-Liao, Kuei-Shu
口試委員:
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 102
中文關鍵詞: 電荷汲引階段性缺陷增生空間缺陷分佈
外文關鍵詞: Charge Pumping, Staged Trap Generation, Spatial Trap Distribution
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  •   為了滿足ITRS元件持續縮小化的要求,一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題,然而在材料替換的過程中,許多問題產生,如電荷捕獲(charge trapping),臨界電壓(threshold voltage)飄移,載子遷移率下降(mobility degradation)等,因此應用在高介電係數閘極介電層電晶體的界面陷阱(interface traps)及氧化層陷阱(oxide traps)可靠度分析因應而生。
      論文中第一部份介紹電荷汲引(charge pumping)技術量測方法。利用電荷汲引量測不同high-κ厚度介電層電晶體的界面陷阱密度與邊緣陷阱密度。描繪出陷阱空間中的分佈以及在矽能隙中能量的分佈情形。
      接著透過分析CVS而產生的臨界電壓飄移隨時間的不同,可發現有缺陷捕捉(trapping)和電應力產生缺陷(stress-induced defects)的階段性區別。其中閘極氧化層缺陷(oxide trap)在臨界電壓的飄移佔了主要成分,所以因電應力而產生的陷阱也較嚴重。建議主要限制元件使用年限(life time)的原因也以改善閘極氧化層缺陷為優先。
      在論文的最後一部分,應用空乏區和變頻的方法結合在電荷汲引技術上,可以用來量測在電晶體接面(junction)邊上三維陷阱密度的分布情形。利用上述的三維量測方法,對電晶體施加CVS和CHCS之可靠度使用條件進行分析。可發現隨所施加的電應力(stress)不同,在空間性上產生的陷阱密度分部情況也有很大的不同。期望在空間性上的瞭解為改善元件特性的製程方法提供方向。


    For satisfy ITRS rule to keep device scale down. General method use high-kapa material which replaced silicon dioxide MOSFET to overcome gate leakage problem. But there are more issues in the process. Such as charge trapping, threshold voltage shift, mobility degradation, et al. Becasue of the problem mentioned, technique to detect interface traps and oxide traps be developed.
    In the first part of thesis, introduce charge pumping technique. Use CP method to measure interface trap and border trap in different gate dielectric thickness MOSFET. To understand the trap energy distribution in silicon bandgap.
    In the second part of thesis, experiment study the Constant-Voltage-Stress which shift threshold voltage in different time. The staged degredation can separate as trapping and stress-induced defects. After, experimental study discover oxide trap dominate the threshold voltage shift in trapping stage. And stress induced trap generation come from oxide trap are more serious. So, improve oxide trap in MOSFET would be first priority to satisfied life time restraint.
    In the last part of thesis, experiment combine depletion region method and frequency method in Charge Pumping technique to measure device's junction side spatial distribution. And use this 3D distribution to detect trap generation after CHCS and PBTI reliability test. Experimental study discover the stress could be different spatial damaged in device. Wish using this knowledge help to improve device.

    摘要 致謝 目錄 圖表目錄 第一章 序論   1.1 研究動機   1.2 高介電係數材料選擇   1.3 電荷汲引量測技術   1.4 論文大綱 第二章 應用電荷汲引量測技術分析High-κ介電層電晶體陷阱分佈   2.1 研究動機   2.2 界面陷阱密度與能量分佈   2.3 邊緣陷阱密度縱深分佈的量測   2.4 結論 第三章 定電壓電應力的階段性陷阱產生研究   3.1 研究動機   3.2 探討定電壓電應力造成階段性的不同現   3.3 定電壓電應力之缺陷捕捉階段現象研究   3.4 利用電荷汲引研究定電壓電應力之傷害階段現象   3.5 結論 第四章 應用電荷汲引結合空乏區之量測技術分析電晶體接面處陷阱    分佈   4.1 研究動機   4.2 電荷汲引閘極脈衝之振幅影響   4.3 電荷汲引探測汲極接面原理   4.4 電荷汲引結合汲極技術之漏電流補償   4.5 結論 第五章 應用電荷汲引結合空乏區之技術在電晶體接面處陷阱的空間    性分佈分析   5.1 研究動機   5.2 結合側邊和縱深探測   5.3 通道熱載子可靠度測試   5.4 正偏壓溫度穩定性可靠度測試   5.5 結論 第六章 結論 參考文獻

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