先進金氧半電晶體之高頻雜訊分析｜國立清華大學博碩士論文庫

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研究生：	楊欣逸 Hsin-Yi Yang
論文名稱：	先進金氧半電晶體之高頻雜訊分析 Analysis of High Frequency Noise in Advanced MOS Transistors
指導教授：	徐碩鴻 Shuo-Hung Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	67
中文關鍵詞：	金氧半場效電晶體之高頻雜訊、雜訊參數、waffle佈局
外文關鍵詞：	MOSFET noise, noise parameters, waffle layout
相關次數：	點閱：2 下載：0
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儘管電子產業技術的不斷進步，金氧半場效電晶體仍為主流應用，而每一代新製程使得通道長度一再縮小，除了提高元件的操作頻率外，高頻雜訊的分析也更趨複雜。現今已有相當多論文探討有關次微米元件的高頻雜訊，所提出的各種現象解釋，公式，和模型等雖有差異，其實多依循相似的原理再進行不同的推導運算而已。另外從次微米元件的雜訊來源來作分析，以往較為次要的來源亦因操作頻率上升而變得不可忽視，在低雜訊電路應用中，該如何降低其高頻雜訊已成為相當重要的課題。
整篇論文裡，我們主要著重在量測與分析高頻雜訊參數。從0.18與0.13微米的多指狀金氧半場效電晶體開始分析起，一方面可以驗證論文的數據與模型，另一方面也發覺雜訊參數之一的noise resistance與整體電路雜訊的高度相關性。而在比較N型與P型兩種電晶體的雜訊效能後，從中得知其特性的相似與差異處，這也提供了電路設計者選擇元件時的考量。之後我們參考論文設計了預期可以降低高頻雜訊的waffle佈局電晶體，將其直流與高頻特性進行完整的分析，發現其特殊佈局確實可以降低電晶體通道的熱雜訊，只要能再配合閘極電阻的降低，將能夠明顯地改善高頻的雜訊表現。

With technology progressing continuously, MOSFETs are utilized extensively in high frequency applications. As the device size scaling down, the analysis of high frequency noise becomes more complicated than that in the conventional long channel devices. Many publications have studied the excess thermal noise and derived the analytical equations from different models. Although the final proposed equations are different, some similar effects such as velocity saturation, channel length modulation and so forth are adopted.
In this study, we set a simple procedure to cope with the experimental data and verify those equations by using standard 0.13-□m and 0.18-□m devices, inclusive of n- and p-channel MOSFETs. Furthermore, we focus on the analysis of the four noise parameters, and observe the similarities and differences of these parameters as functions of both the frequency and bias voltage. Such as biasing adequate voltage corresponding to different devices can achieve their optimized performance. At last, the waffle-type layout MOSFET which is expected to possess lower high frequency noise has been designed. We investigate the high frequency noise characteristics with different device layouts. The waffle configuration reduces its channel thermal noise compared with multi-finger type about 30-47% at different frequencies and bias voltages. The noise resistance is also decreased by 9%. Moreover, the gates of waffle device can be connected on both sides to reduce gate resistance to improve its noise performance.

Table of Contents

Abstract    i
Acknowledgement    iii
List of Tables    vi
List of Figures    vii

CHAPTER 1  INTRODUCTION    1
1.1    Motivation    1
1.2    Overview    2

CHAPTER 2  FUNDAMENTALS OF THERMAL NOISE IN MOSFETS    3
       2.1 Introduction to thermal noise    3
       2.2 Thermal noise in deep submicron MOSFETs    4
          2.2.1 Velocity saturation    5
          2.2.2 Carrier heating effect    6
          2.2.3 Channel length modulation    6
          2.2.4 Gate resistance noise    7
          2.2.5 Substrate noise    8
       2.3 Analytical noise model and equations    9

CHAPTER 3  NOISE DE-EMBEDDING.    13
       3.1 Correlation matrix of the noisy two-port network    13
          3.1.1 Fundamentals of the correlation matrix    14
          3.1.2 Properties of the correlation matrix    15
          3.1.3 Correlation matrix relative to noise parameters    16
       3.2 Simple flow of noise de-embedding    18
       3.3 Comparison between pre- and post-de-embedded data    20
       3.4 Summary    23

CHAPTER 4  ANALYSIS OF MULTI-FINGER MOSFETS    24
       4.1 Specification of devices under test and experimental procedure    24
       4.2 Noise parameters of 0.13-□m and 0.18-□m MOSFETs    26
          4.2.1 Analysis of multi-finger NMOS and PMOS by 0.18-□m technology    26
          4.2.2 Analysis of multi-finger NMOS and PMOS by 0.13-□m technology    31
          4.2.3 Comparison between multi-finger NMOS and PMOS    35
       4.3 Simulation of noise parameters with analytical equations    38
       4.4 Summary    42
CHAPTER 5  ANALYSIS OF WAFFLE MOSFETS    43
5.1 Design and layout of waffle MOSFETs    43
       5.2 DC performance    46
       5.3 High frequency noise performance    50
          5.3.1 The drain current spectral density    51
          5.3.2 Experimental noise parameters    53
       5.4 Summary    60

CHAPTER 6  CONCLUSIONS    61
       6.1 Summary    61
       6.2 Recommendations for future work    63

BIBLIOGRAPHY    64


List of Tables

Table 1. Specifications of 0.18-□m devices    25
Table 2. Specifications of 0.13-□m devices    25
Table 3. Specifications of 60 □m waffle devices    47





















List of Figures

Fig. 2.1 Cross section of a MOSFET channel divided into a gradual channel region (I)
and a velocity saturation region (II) [3]    7

Fig. 2.2 (a) Equivalent compact circuit model of MOSFET with thermal noise sources,
where SiG and SiD represent the induced gate and drain current noise, and the
other noise current source 4kTRg is generated from gate resistance. (b) The
noise free compact circuit model of MOSFET with input referred noise voltage
and current [19]    10

Fig. 3.1 Schematic diagrams of noise equivalent networks: (a) impedance representation;
(b) chain representation    14

Fig. 3.2 Noise model for calculating the amplifier noise figure    17

Fig. 3.3 Noise parameters versus frequency for the 0.13-□m NMOS at VGS = 0.5, 0.85
V, and VDS = 1 V: (a) minimum noise figure NFmin, (b) noise resistance Rn, (c) magnitude of the optimum source reflection coefficient |Гopt|, (d) phase of the optimum source reflection coefficient∠Гopt    21

Fig. 3.4 Noise parameters versus frequency for the 0.13-□m PMOS at VGS = -0.5, -0.85
 V, and VDS = -1 V: (a) minimum noise figure NFmin, (b) noise resistance Rn, (c) magnitude of the optimum source reflection coefficient |Гopt|, (d) phase of the optimum source reflection coefficient∠Гopt    22

Fig. 4.1 Noise parameters versus frequency for the 0.18-□m NMOS at VGS = 0.7, 1.1,
1.5 V, and VDS = 1.8 V: (a) minimum noise figure NFmin, (b) noise resistance
Rn, (c) magnitude of the optimum source reflection coefficient |Гopt|, (d) phase
of the optimum source reflection coefficient ∠Гopt, (e) NF50. Graphs on the left
side whose total width equal 80 □m, and 96 □m devices are shown on the right
side    28

Fig. 4.2 Noise parameters versus frequency for the 0.18-□m PMOS at VGS = -0.7, -1.1,
-1.5 V, and VDS = -1.8 V: (a) minimum noise figure NFmin, (b) noise resistance
Rn, (c) magnitude of the optimum source reflection coefficient |Гopt|, (d) phase
of the optimum source reflection coefficient ∠Гopt, (e) NF50. Graphs on the left
side whose total width equal 80 □m, and 96 □m devices are shown on the right
side    30

Fig. 4.3 Noise parameters versus frequency for two parallel NMOS in 0.13-□m generation
at VGS = 0.5, 0.7, 0.85 V, and VDS = 1 V: (a) NFmin, (b) Rn, (c) |Гopt|, (d)∠Гopt,
(e) NF50    33
Fig. 4.4 Noise parameters versus frequency for two parallel PMOS in 0.13-□m generation
at VGS = -0.5, -0.7, -0.85 V, and VDS = -1 V: (a) NFmin, (b) Rn, (c) |Гopt|, (d)∠Гopt,
(e) NF50    34

Fig. 4.5 Noise parameters versus |VGS| for the 0.18-□m NMOS and PMOS whose
total width are 80 □m at VDS = 1.8 V: (a) NFmin, (b) Rn, (c) |Гopt|, (d)∠Гopt,
(e) NF50. Graphs on the left side are measured at 4 GHz, and at 16 GHz on
the right side    36

Fig. 4.6 Noise parameters versus frequency for the 0.18-□m NMOS whose total width
is 80 □m at VGS = 1 V, VDS = 1.8 V: (a) NFmin, (b) Rn, (c) |Гopt|, (d)∠Гopt,
(e) NF50. “Measure” means the measurement data after de-embedding, and
“Model” means the results from analytical equations with different γ value    39

Fig. 4.7 Noise parameters versus frequency for the 0.18-□m PMOS whose total width
is 80 □m at VGS = -1 V, VDS = -1.8 V: (a) NFmin, (b) Rn, (c) |Гopt|, (d)∠Гopt,
(e) NF50. “Measure” means the measurement data after de-embedding, and
“Model” means the results from analytical equations with different γ value    40

Fig. 4.8 γ value versus |VGS| for the 0.18-□m NMOS and PMOS whose total width
is 80 □m at |VDS| = 1.8 V    41

Fig. 5.1 Two kinds of unit cell configurations for n-by-n waffle MOSFETs:
(a) 3-by-3, (b) 5-by-5    44

Fig. 5.2 The layouts of two kinds of 3-by-3 waffle MOSFETs: (a) 1 contact in one source/drain diffusion region, (b) 4 contacts in one source/drain diffusion
region    45

Fig. 5.3 The layout of the multi-finger MOSFET provided from foundry.    45

Fig. 5.4 The DC I-V characteristics for different kinds of n-type MOSFETs biased
at VGS equals 0.6, 0.8, and 1 V. “NMOS1” means the 3-by-3 waffle NMOS, “NMOS2” means the 5-by-5 waffle NMOS, and “NMOS3” means the
multi-finger NMOS    47

Fig. 5.5 The comparison of DC I-V characteristics in different configurations of
waffle NMOS whose total gate width are designed to 60 □m: (a) comparison between NMOS1, 2, 3, and 4. (b) comparison between NMOS1, 5, 6    48

Fig. 5.6 The layouts of different devices under test which are used to verify the STI
effect originated from isolation field oxide    49

Fig. 5.7 The drain current spectral density SiD versus frequency at VGS = 1 V, and VDS =
1.8 V    52

Fig. 5.8 The drain current spectral density SiD versus VGS at frequency = 10 GHz,
and VDS is fixed to 1.8 V    52

Fig. 5.9 Noise resistance Rn versus frequency at VGS = 1 V, and VDS = 1.8 V    54

Fig. 5.10 Gate resistance Rg versus frequency at VGS = 1 V, and VDS = 1.8 V    55

Fig. 5.11 Minimum noise figure NFmin versus frequency at VGS = 1 V, and VDS = 1.8 V    57

Fig. 5.12 Real part of the optimum source admittance Gopt versus frequency at VGS =
1 V, and VDS = 1.8 V    58

Fig. 5.13 Imaginary part of the optimum source admittance Bopt versus frequency at
VGS = 1 V, and VDS = 1.8 V    58

Fig. 5.14 NF50, the noise figure when signal source is connected directly with 50 Ω impedance, versus frequency at VGS = 1 V, and VDS = 1.8 V    59

                                

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