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研究生: 詹宗晟
論文名稱: 電遷移效應對銅薄膜表面粗糙度影響之研究
A Study of Effect of Electromigration on Surface Roughness of Copper Thin Film
指導教授: 廖建能
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 材料科學工程學系
Materials Science and Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 57
中文關鍵詞: 銅導線平坦化電遷移銅製程表面粗糙度
外文關鍵詞: copper interconnect, planarization, electromigration, copper metallization, surface roughness
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  • 在銅製程中,銅晶種層的表面粗糙度對於之後的電鍍銅導線性質會有很密切的影響。隨著電子元件的不斷縮小,到了45奈米製程節點,銅晶種層的厚度會下降到30-50奈米且其表面粗糙度需低於1奈米。然而在本實驗中,銅薄膜在200 °C退火1分鐘之後,其表面粗糙度會高達7.5奈米。在電鍍過程中,ㄧ個表面粗糙的銅晶種層會在銅晶種層跟電鍍銅導線之間產生孔洞,進而造成元件可靠度下降的問題。在本研究中,我們利用電致遷移的方法,試圖改善銅薄膜的表面粗糙度。藉由原子力顯微鏡的分析結果,我們發現在通電流30分鐘之後,銅薄膜的表面粗糙度由原本的7.5奈米下降至4奈米,在通電流10小時之後,銅薄膜的表面粗糙度更進一步下降至1.4奈米,這個現象可藉由表面晶粒薄化(grain thinning)來解釋。另外,一般來講,施加交流電通過金屬薄膜並不會造成任何電致遷移的現象發生,然而在本實驗中,我們發現施加交流電通過銅薄膜也可讓其粗糙度下降,這部份推測與棘輪作用(ratchet effect)有關。


    For conventional copper (Cu) damascene processes employed in integrated-circuits fabrication technology, a seed layer is required prior to electroplating of copper metallization. As a result, the surface roughness of the seed layer is expected to affect the structure and quality of the electroplated Cu layer. For 45 nm technology node, the thickness of Cu seed layer will be 30-50 nm with less than 1 nm surface roughness. However, the surface roughness of Cu films after annealing at 200 °C for 1 minute would be 7.5 nm. A rough Cu surface would cause voiding problem between Cu seed layer and electroplated Cu, leading to electromigration reliability issue. In the present study, we have proposed a method to improve the surface roughness of copper thin films by electric current induced surface smoothing. Due to fast surface diffusion of copper atoms, the surface morphology of copper thin film can be modified by electrical current induced atomic migration. Our results show that the surface morphology and film texture of the electrically stressed Cu thin films change notably with time according to the atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The roughness of copper thin film was found to improve from the initial 7.5 nm to 4 nm after 30-minute electrical current stressing, and eventually down to 1.4 nm after 10 hours of electrical current stressing. In general, no long range mass transport is expected for metal films stressed by alternating electrical current. However, the surface roughness of Cu films is reduced after alternating electrically stressing. The mechanism of electric current induce surface smoothing is speculated to be related to the ratchet effect.

    致謝 I Abstract in Chinese II Abstract……………………………………………………………………………II Contents .......IV List of Figures VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Objective 2 1.3 Organization of thesis 3 Chapter 2 Literature review 4 2.1 Seed layer depositing method 4 2.1.1 Seed layer deposited by chemical vapor deposition 6 2.1.2 Seed layer deposited by atomic layer deposition 8 2.1.3 Seed layer deposited by electroless deposition 8 2.1.4 Diffusion barrier / adhesion layer as seed layer 9 2.2 Roughening mechanism during deposition 10 2.3 The nucleation extrusion zones 13 2.4 Electromigration physics 14 2.4.1 Theory of electromigration 16 2.4.2 Effect of microstructure on Cu electromigration 19 2.4.3 Application of electromigration 23 Chapter 3 Experimental procedure ……..25 3.1 Specimen preparation 25 3.2 Experimental setup 26 3.3 Analyses techniques 28 3.3.1 X-ray diffractometry 28 3.3.2 Atomic force microscopy 28 Chapter 4 Results and discussions 30 4.1 Evolution of surface morphology of Cu thin film during annealing 30 4.2 Effect of electrical current stressing on surface morphology and texture of Cu films………………………………………………..…..37 4.2.1 Evolution of surface morphology and texture of Cu films after electrical current stressing……………………..……………........37 4.2.2 Grain thinning mechanism…………….………………….…........41 4.2.3 Effect of alternating electrical current on surface morphology…..45 Chapter 5 Conclusions 50 5.1 Conclusions………………….………….…………….………….........50 5.2 Future works………………………50 References 52 List of Figures Figure 2-1 Types of evolution in Cu damascene plating profile 5 Figure 2-2 SEM photographs of filling experiments in different filling condition, (A) Voided filling, (B) Void-free filling, and (C) Seam type voided filling 6 Figure 2-3 Comparison of conventional and seedless barrier processes 10 Figure 2-4 STM images of the first derivative measured for deposition at different thicknesses and temperature, 299 K 12 Figure 2-5 Schematic of the cross-section of a vicinal surface (lower panel) containing two monatomic steps and the asymmetric lattice potential (upper panel) experienced by the atoms (gray circles) diffusing on this surface. Note that a non-zero Schwoebel barrier, Eb, is necessary to break the spatial symmetry of the potential 12 Figure 2-6 A schematic representation of the deformation of the electric field around a granular defect on a substrate………………………………. .14 Figure 2-7 TEM image showing a large EM-induced void at the cathode end of a 60nm wide Cu wire 15 Figure 2-8 TEM image showing void at the cathode end and extrusion at the anode end for a Cu wire under electrical current stressing 15 Figure 2-9 The dependence of EM lifetime on microstructure of Al-based interconnects 22 Figure 2-10 The schematic diagrams of void growth mechanisms: (a) edge displacement and (b) surface grain thinning. The direction of electron flow is from right to left. Arrows with the dotted lines show the migration of Cu atoms 22 Figure 2-11 (a) Al nanowire from a 0.5-μm-square slot penetrating the passivation layer and (b) Al nanowire from a 0.2-μm-square slot not penetrating the passivation layer 24 Figure 2-12 Unzipping model of evolution of a nanogap during FCE. (a) Starting with the initial wire, an edge atom is thermally excited. (b) This atom is easily transported away by the applied current along the high-mobility [110] directions. (c) The edge vacancy allows adjacent atoms to easily electromigrate and jump to the edge due to their reduced number of nearest neighbors. (d) The edge is thus unstable once theunzipping of a layer begins 24 Figure 3-1 The scheme of experimental process 26 Figure 3-2 Schematic diagram of an electric current passing through the Cu stripe using electrical probe 27 Figure 4-1 AFM image showing the surface morphology and surface roughness of as-deposited Cu thin film 34 Figure 4-2 AFM image showing the surface morphology of Cu thin film after annealing for 1 minute at different temperature. (a) 200°C, (b) 250°C, (c)300°C, (d) 400°C 34 Figure 4-3 AFM image showing the surface morphology of Cu thin film after annealing for 2 minutes at different temperature. (a) 200°C, (b) 250°C, (c) 300°C, (d) 400°C 35 Figure 4-4 Texture map calculated with surface/interface and elastic strain energy for Cu-film resulting from grain growth at temperature Tgg in Cu films of thickness h, deposited at Tdep 36 Figure 4-5 Schematic diagram of grain boundary migration due to Cu atoms diffuse from (110)-textured grain to (111)-textured grain driven by surface energy minimization………………………………………… 36 Figure 4-6 AFM images showing the surface morphology of the Cu thin film after electrical current stressing for different times. (a) none ; (b) 10 min ; (c) 30min ; (d) 1hr ; (e) 5hrs; (f) 10hrs 39 Figure 4-7 The surface roughness values of Cu thin film after electrical current stressing for different times 40 Figure 4-8 The X-ray diffraction spectra for a Cu thin film at different stages during electric current stressing 40 Figure 4-9 AFM image showing the surface morphology of annealed Cu thin film after annealing at 100 °C in 1 hour again. (a) annealed at 200 °C in 2mins ;(b) the same as (a) except additionally annealing at 100 °C in 1 hour again ;(c) annealed at 250 °C in 2mins ;(d) the same as (c) except additionally annealing at 100 °C in 1 hour again 41 Figure 4-10 Schematic diagram of grain thinning mechanism 44 Figure 4-11 Shematic diagram of grain thinning mechanism in {111}-oriented grain 44 Figure 4-12 AFM image showing the surface morphology of Cu thin film after stressing electrical current. (a) without stressing; (b) with stressing an direct current in 1 hour ;(c) with stressing an alternating current with 100Hz in 1 hour ;(d) with stressing an alternating current with 1000Hz in 1 hour 47 Figure 4-13 AFM image showing the surface morphology of Cu thin film after stressing electrical current. (a) without stressing; (c) with stressing an direct current in 1 hour; (e) with stressing an alternating current with 1000Hz in 1 hour; (b), (d), and (f) are scan lines indicated in (a), (c), and(e), respectively 48 Figure 4-14 Ratchet effect. (a) Shoewel barrier potential for a given stepped surface. (b) When an external field is applied, the minimum located at points b (descending surface slope) are deeper than that those at a (ascending surface slope). (c) When reversing the electric field, the minimum distribution also changes, and now, the deeper minimum is located at point b’ 49

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