隨著互補式金屬氧化物半導體製程技術進入深次微米時代，製程變異以及生
產過程缺陷嚴重得影響著產品的良率，截至目前為止，並沒有一套有效率的方法
去輔助設計者分析製程變異所帶來的影響。製程變異主要分成兩種，隨機性製程
變異以及系統性製程變異，其中系統性製程變異對於光罩、蝕刻與佈局有很高的
相依性，我們針對系統性變異來加以分析。
在本篇論文中，我們提出一套多重時脈測試的方法，先挑取受到系統性製程
變異影響的路徑，在利用多重測試時脈加以區分晶片，再使用分群的方法，將受
到相似製程變異的晶片分群再一起，並應用了SAT-based 的方法找到相對應調整
過後的電壓值，並建立分類器，去修復受到製程變異影響造成無法達到標準的晶
片，由於SAT-based 的方法需要更大量的測試時脈，所以使用建立分類器的方法
只需要2~3 個測試時脈可以大量節省測試成本(約省下原來的90%)並同時達到接
近SAT-based 的良率。
利用調整電壓來加速晶片已達到修復目的，勢必會造成電量上的消耗，
但經過我們的實驗結果顯示，只要利用2 到3 個測試時脈，就可以達到88%~99%
的良率，而且電量消耗只多出4%~25%，相較於最差的情況(所有列電壓都拉高)
需額外增加50%電量，我們的方法可以找到較低的電量消耗就可以達到很高的良
率。

[1] M. Choi and L. Milor, “Impact on circuit performance of deterministic within-die variation
in nanoscale semiconductor manufacturing,” IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, 2006.
[2] K. Bowman, S. Duvall, and J. Meindl, “Impact of die-to-die and within-die parameter fluctuations
on the maximum clock frequency distribution for gigascale integration,” IEEE Journal
of Solid-State Circuits, 2002.
[3] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations
and impact on circuits and microarchitecture,” ACM/IEEE Design Automation Conference,
2003.
[4] H. Aikawa, T. Sanuki, A. Sakata, E. Morifuji, H. Yoshimura, T. Asami, H. Otani, and H. Oyamatsu,
“Compact Model for Layout Dependent Variability,” in International Electron Devices
Meeting, 2009.
[5] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive
body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor
frequency and leakage,” IEEE Journal of Solid-State Circuits, 2002.
[6] J. Gregg and T. Chen, “Post Silicon Power/Performance Optimization in the Presence of
Process Variations Using Individual Well-Adaptive Body Biasing,” IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 2007.
[7] J. Gregg and T. chen, “Optimization of individual well adaptive body biasing (IWABB) using
a multiple objective evolutionary algorithm,” International Symposium on Quality of Electronic
Design, 2005.
[8] T. Chen and J. Gregg, “A low cost individual-well adaptive body bias (IWABB) scheme
for leakage power reduction and performance enhancement in the presence of intra-die variations,”
Proceedings of the Design, Automation and Test in Europe Conference and Exhibition,
2004.
[9] M. Elgebaly and M. Sachdev, “Variation-Aware Adaptive Voltage Scaling System,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, 2007.
[10] S. Theodoridis and K. Koutroumbas, Pattern Recognition. Elsevier Science, 2008, sec. 12.4.
[11] J.-H. Kuo, T.-S. Hsu, and J.-J. Liou, “Test cost reduction for performance yield recovery by
classification of multiple-clock test data,” in Proc. ATS’12, 2012, pp. 320–325.
[12] C.-C. Chang and C.-J. Lin, LIBSVM: a library for support vector machines, 2001, software
available at http://www.csie.ntu.edu.tw/cjlin/libsvm.
[13] Y.-Y. Chen and J.-J. Liou, “A non-intrusive and accurate inspection method for segment delay
variabilities,” Proceedings of IEEE Asian Test Symposium, 2009.
[14] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda,
“Statistical delay computation considering spatial correlations,” Proceedings of Asia & South
Pacific Design Automation Conference, 2003.
[15] M. Chun-Chia Chen, “Design Methodology and Simulation Framework for Variation-Aware
Cell-based Tunable Circuits,” 2008.
[16] J.-J. Liou, Y.-Y. Chen, C.-C. Chen, C.-Y. Chien, and K.-L. Wu, “Diagnosis-assisted Supply
Voltage Configuration to Increase Performance Yield of Cell-Based Designs,” Proceedings
of Asia & South Pacific Design Automation Conference, 2011.
[17] L.-T. Wang, C. E. Stroud, and N. A. Touba, System-on-Chip Test Architectures: Nanometer
Design for Testability. Morgan Kaufmann, 2007.
[18] J. jia Liou, A. Krstic, L.-C. Wang, and K. ting Cheng, “False-path-aware statistical timing
analysis and efficient path selection for delay testing and timing validation,” Proceedings of
Design Automation Conference, 2002.
[19] C.-W. Hsu and C.-J. Lin, “A comparison of methods for multiclass support vector machines,”
IEEE Transactions on Neural Networks, 2002.
[20] B. Brumen, T.Welzer, I. Rozman, M. Holbl, and H. Jaakkola, “Convergence detection criteria
for classification based on final error rate,” IEEE International Conference on Computational
Cybernetics, 2005.
[21] B. Brumen, M. B. Juriˇc, T. Welzer, I. Rozman, H. Jaakkola, and A. Papadopoulos, “Assessment
of classification models with small amounts of data,” Informatica, 2007.
[22] B. Brumen, I. Golob, H. Jaakkola, T. Welzer, and I. Rozman, “Early assessment of classification
performance,” in Proceedings of the second workshop on Australasian information
security, Data Mining and Web Intelligence, and Software Internationalisation - Volume 32,
2004.
[23] C. D. Manning, P. Raghavan, and H. Sch¨utze, Introduction to information retrieval. Cambridge
University Press Cambridge, 2008, vol. 1, sec. 16.3.