使用多重工作電壓和多重臨界電壓伴隨邏輯閘置換的設計是一種達到低功率的有效方法。我們提出了一個貪婪的方法，同時考慮工作電壓和臨界電壓伴隨邏輯閘置換並且把電位移轉器納入考量，可以有效的去降低功率消耗。我們的實驗結果可以證明我們的演算法在中活性與低活性裡，分別可以減少36.3% 和35.2% 的功率消耗。和一個分成兩階段的演算法作比較，我們在中活性與低活性裡，也分別可以比他們的演算法減少4.2% 和9.7% 的功率消耗。最後，因為我們是同時考慮工作電壓和臨界電壓伴隨邏輯閘置換，導致執行時間非常久，所以我們提出了一個靜態調整的方法和一個動態調整的方法有效的降低執行時間。

One of the most e®ective way to achieve low power is using multiple supply votages and multiple threshold voltages with gate sizing for modern ASIC designs. We propose a sensitivity based approach to minimize the total power consumption using simultaneous Vdd and Vth voltage assignment with gate sizing that take the level shifters into consideration. The experimental results show that our algorithm can obtain 36.3% and 35.2% average total power savings for nominal primary input activity and low primary input activity, respectively. Compared with a two stage Vdd
and Vth voltage assignment with gate sizing algorithm in [13], our algorithm also consume 4.2% and 9.7% less average total power than it. Finally, since we perform Vdd and Vth assignment simultaneously, it makes the total runtime very long. So we propose a static adjustment and a dynamic adjustment approaches to reduce the total runtime of our algorithm.

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[17] ISCAS-95 testbenchs,
http://www.fm.vslib.cz/~kes/asic/iscas/