MPEG-1/2/4、H.264以 及 VC-1 是很廣泛被應用的影像壓縮系統。在本篇論文中我們使用了多層次共用因子 (Multi-level Factor Share) 以及分散式算數 (Distributed Arithmetic) 來建構多重標準之低成本 DCT ( Discrete Cosine Transform )與 IDCT ( Inverse Discrete Cosine Transform ) 運算。此架構可以支援四種型式的運算，包括 8 x 8 、8 x 4 、4 x 8 以及 4 x 4 轉換。我們利用多層次共用因子和分散式算數來共用係數矩陣電路，利用加法器 (Adder) 以及移位器 (Shifter) 取而代乘法器。不僅大幅降低係數乘法運算中的重複片段，還進一步減少加法樹 (Adder Tree) 之所需加法器之數量，如此節省面積之消耗。此外，我們利用 DCT 與 IDCT 其係數矩陣的相似性質，在電路中以時間交錯的方式重複使用同一塊係數矩陣電路。不僅降低正向與逆向餘弦運算所需之面積成本，還可以同時運行 DCT 與 IDCT 轉換，維持高輸出率( Throughput Rate )，滿足即時 (Real-Time) 影像編碼的需求。而透過轉置記憶體( Transpose Memory )的轉換，我們可以將資料重新排序輸出二維資料，並且使用SORT1、iSORT1電路加以排序，讓一維與二維資料可以分時交錯並且重複使用 1-D 核心，即使用一個1-D核心同時運算 DCT 與 IDCT 之一維與二維資料。如此整個架構中僅需要33個加法器即可完成所有運算。其中 MPEG-4 IDCT 可以滿足 IEEE 1180-1990 之精確度要求，各標準運算之 PSNR 也都有到50~60 dB 之間，為高精確度之多標準處理。透過 TSMC 0.18-um 的電路合成，在 Slow Model 下可以達到 227 MHz 之操作頻率，且面積 32K 的邏輯閘可以達到 454 M pixel/sec 之輸出率，如此便可以支援 HDTV (1920 x 1080P@60Hz) 之規格。

Video and Image compression standard, such as MPEG-1/2/4、H.264 and VC-1, are widely used in video and image applications. In this thesis, multi-level factor share and distributed arithmetic are being used to build multi-standard DCT (Discrete Cosine Transform) and IDCT (Inverse Discrete Cosine Transform) transforms. The proposed architecture can process four transform types, including 8 x 8、8 x 4、4 x 8 and 4 x 4 transforms. We use multi-level factor share and distributed arithmetic to share the coefficient matrix circuits and we replace the multipliers with the adders and shifters. The result not only reduces the number of redundant parts in coefficients multiplication, but further reduces the needed adders in adder trees and leads to a low-cost design. Besides, based on the similarities of DCT and IDCT transforms, we reuse the same circuits to manipulate DCT and IDCT by interlaced sorting methods. Not only the cost of area is saved, but DCT and IDCT are also operated simultaneously to reach the high throughput rate and meet the demands of real-time system. By using the transpose memory, we are able to transpose the 1-D results into the 2-D input data. With SORT1 and iSORT1circuits, we further arrange the data of 1-D and 2-D in orders which will allow us to reuse the same 1-D core to compute 2-D data . That means we can compute DCT and IDCT’s 1-D and 2-D data in the same time with only one 1-D core. In this way, only 33 adders are needed to achieve the whole computations. The proposed Architecture can meet the precision of IEEE 1180-1990 MPEG-4 IDCT and get to high peak signal to noise ratio (about 50~60 dB) between different standards. We use TSMC 0.18-um process to implement this chip. The operating frequency will reach 227MHz in slow model and achieve 454MHz throughput rate with only 32K gate counts. In this manner, it can support HDTV (1920 x 1080P@60Hz) spec.

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