為了提升高頻金氧半場效電晶體在高速通訊系統中的效能，通道長度和閘極厚度必須不斷地縮小。然而當電晶體不斷縮小的過程當中，許多負面的效應也會出現，像是漏電流的增加與低頻雜訊的上升。尤其是低頻雜訊的增加在高速通訊系統當中更為重要，因為低頻雜訊對於射頻電路的特性有相當顯著的影響，同時也限制住電路的偵測靈敏度。
此篇論文，會整理與介紹許多電晶體的基本雜訊，像是熱雜訊..等等。而Flicker雜訊產生的機制與模型將會做較為詳細的介紹。因為淺溝槽隔離是此篇論文探討的重點，所以淺溝槽隔離的製程方法對於金氧半場效電晶體直流與低頻雜訊的影響也將有完整的整理與介紹。同時從過去參考文獻的研究，我們也將說明為何此篇論文要設計對稱與不對稱邊界延伸的結構設計。
而本篇論文0.13微米特殊結構元件的直流量測結果，顯示出淺溝槽隔離對於元件移動率與臨界電壓有相當程度的影響。同時由「對稱延伸結構」的低頻雜訊量測結果，我們可以得知淺溝槽隔離確實會嚴重影響低頻雜訊特性，同時由不同延伸長度的量測，我們可以得知1-2微米的延伸既可達到相當程度的雜訊降低與穩定作用。而「不對稱延伸結構」的量測，讓我們更深入地探討淺溝槽隔離在源極與汲極對於低頻雜訊不同的效應，而最後我們將證明當元件操作於飽和區間，源極端會是雜訊的主要來源。

To improve the performance of high frequency CMOS integrated circuits for achieving high-speed communication systems, the channel length and gate insulator thickness in MOSFET transistors are continuously scaled down. However, as the dimension keeps reducing, many undesired effects appear such as the increase of leakage current and the low frequency noise. In particular, the low frequency noise (also called flicker noise) becomes an important consideration, since the low frequency noise has a severe impact on the phase noise in RF and mixed-mode circuits, and it also limit the information capacity and detection sensitivity.
In this thesis, many basic noise sources in semiconductor devices are reviewed including thermal noise, shot noise, etc. The flicker noise mechanisms and models are discussed in details. Because shallow trench isolation (STI) is the main factor focused in this thesis, STI effect on advanced CMOS characteristics will be discussed, including DC and noise characteristics, from some previous studies and STI properties we will show why we present the symmetric and asymmetric edge-extended layout design.
The 0.13μm RF CMOS on chip measurement results are presented. For DC part demonstration, device Vth、Gm and ID which shifted by STI effect all will be included. By symmetric extending the distance between STI edge and the gate channel, the noise value and variation of devices flicker noise were reduced significantly. Under a fixed VDS of 0.7 V and VGS of 0.6 V, the edge extension devices (W/L= 1/0.13, extension distance= 1.2μm) showed a reduced noise current spectral density variation (SID/I2 ranges from 8.45□10-12 to 2.16□10-11 Hz-1 at 100 Hz) to only ~ one percent of that for devices without edge extension (SID/I2 ranges from 2.0□10-10 to 6.12□10-12 Hz-1 at 100 Hz). The noise improvement level depended on the edge extension values was experimentally investigated and measurement results showed that the impact of stress and traps introduced by STI on device flicker noise can be described by the carrier number with correlated mobility model. This study also indicated that the trend of STI effect on NMOS and PMOS noise performance is the same. In addition, when the devices are biased in saturation region the noise characteristics of asymmetric edge extension devices indicated that STI imperfect effect on source side is the main origins to degrade noise performance.

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